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drm/i915/gvt: add sprite plane flip done support. 

* Add flip done event support for sprite plane on SKL platform.
* Fix bug #1452, "Call Trace:handle_default_event_virt+0xef/0x100
[i915]" while booting up guest.

Signed-off-by: Xu Han <xu.han@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Xu Han 2017-02-14 14:50:47 +08:00 committed by Zhenyu Wang
parent 6294b61ba7
commit 6e27d51457
2 changed files with 23 additions and 1 deletions
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20
drivers/gpu/drm/i915/gvt/cmd_parser.c
View File

@ -1135,6 +1135,8 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
u32 dword2 = cmd_val(s, 2);
u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
info->plane = PRIMARY_PLANE;
switch (plane) {
case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
info->pipe = PIPE_A;
@ -1148,12 +1150,28 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
info->pipe = PIPE_C;
info->event = PRIMARY_C_FLIP_DONE;
break;
case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
info->pipe = PIPE_A;
info->event = SPRITE_A_FLIP_DONE;
info->plane = SPRITE_PLANE;
break;
case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
info->pipe = PIPE_B;
info->event = SPRITE_B_FLIP_DONE;
info->plane = SPRITE_PLANE;
break;
case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
info->pipe = PIPE_C;
info->event = SPRITE_C_FLIP_DONE;
info->plane = SPRITE_PLANE;
break;
default:
gvt_err("unknown plane code %d\n", plane);
return -EINVAL;
}
info->pipe = PRIMARY_PLANE;
info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
info->tile_val = (dword1 & GENMASK(2, 0));
info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;

4
drivers/gpu/drm/i915/gvt/interrupt.c
View File

@ -588,6 +588,10 @@ static void gen8_init_irq(
SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
}
/* GEN8 interrupt PCU events */