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drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices 

If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
This commit is contained in:
Alex Deucher 2011-05-20 12:36:12 -04:00 committed by Dave Airlie
parent d291767b60
commit 6f15c506e0
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/radeon/atombios_crtc.c
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@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v3.ucPostDiv = post_div;
args.v3.ucPpll = pll_id;
args.v3.ucMiscInfo = (pll_id << 2);
if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
args.v3.ucTransmitterId = encoder_id;
args.v3.ucEncoderMode = encoder_mode;
break;