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drm/amd/display: Add unknown clk state. 

[Why]
System hang during S0i3 if DP only connected due to clk is disabled when
doing link training.
During S0i3, clk is disabled while the clk state is updated when ini_hw
called, and at the moment clk is still disabled which indicating a wrong
state for next time trying to enable clk.

[How]
Add an unknown state and initialize it during int_hw, make sure enable clk
command be sent to smu.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2019-09-26 14:08:41 -04:00 committed by Alex Deucher
parent 123c53a97a
commit 6f29c3588b
3 changed files with 12 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View File

@ -114,22 +114,22 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
*/ */
if (safe_to_lower) { if (safe_to_lower) {
/* check that we're not already in lower */ /* check that we're not already in lower */
if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) { if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
display_count = rn_get_active_display_cnt_wa(dc, context); display_count = rn_get_active_display_cnt_wa(dc, context);
/* if we can go lower, go lower */ /* if we can go lower, go lower */
if (display_count == 0) { if (display_count == 0) {
rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_OPTIMIZED); rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
/* update power state */ /* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_OPTIMIZED; clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
} }
} }
} else { } else {
/* check that we're not already in the normal state */ /* check that we're not already in D0 */
if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) { if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_NORMAL); rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
/* update power state */ /* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL; clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
} }
} }
@ -393,7 +393,7 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
// Assumption is that boot state always supports pstate // Assumption is that boot state always supports pstate
clk_mgr->clks.p_state_change_support = true; clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true; clk_mgr->clks.prev_p_state_change_support = true;
clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL; clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
} }
static struct clk_mgr_funcs dcn21_funcs = { static struct clk_mgr_funcs dcn21_funcs = {

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
View File

@ -170,7 +170,7 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
{ {
int disp_count; int disp_count;
if (state == DCN_PWR_STATE_OPTIMIZED) if (state == DCN_PWR_STATE_LOW_POWER)
disp_count = 0; disp_count = 0;
else else
disp_count = 1; disp_count = 1;

5
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -257,8 +257,9 @@ enum dtm_pstate{
}; };
enum dcn_pwr_state { enum dcn_pwr_state {
DCN_PWR_STATE_OPTIMIZED = 0, DCN_PWR_STATE_UNKNOWN = -1,
DCN_PWR_STATE_NORMAL = 1 DCN_PWR_STATE_MISSION_MODE = 0,
DCN_PWR_STATE_LOW_POWER = 3,
}; };
/* /*