A single commit to make the vector allocation code more resilent against an

accidental allocation attempt for IRQ2.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmCGipQTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoZ+AD/9cLoIs2Gqn5Yy8JQb2L7DCuASFOvCQ
 AW5BcetMnj9FCRzS0SIWUX31nwSHMnoLOu+yPglOPxpZZRVHlOmf8mxW7ew9SACH
 KiAbIsvrHlKnuDX5TPFV/BwqSo4qBW/lsD7DFeVJHqSAWZMm++NsqICCaGOiCz+X
 MAt7L7IpMVKlrKYohw9KrOlb0C9+xMD1AJKB9gyuAoZrzEcuX6RVxXK2GtzXYMq8
 jsf+0gbwk8OT77CYPHYffBVSb2gD2+LSS4tMXEurlbxhXC+A8p+ooM79RysdAPkn
 Xz7letJC3nKD7nCFcrTheFko7wXdmCZFIelFghYV2q3OVsDXXsX0t/StA5Ag/oLm
 RwDxmbMtyY8dYlYS3cmpsWatpe5lAAQOYHRf2lSxHyxXGj9JT8I8n21f1zC7n0hP
 tQSJRKpD5uyFjEg+vmtwJ4VyxM7hY/NTpykXwAZVTF7c7XhJZhu7b+PzIxfr0zgo
 yjP6vvnejwwlydDUkt8f0ujNRVO1KFxJbJn3rP7920VcqXpQxmDW2X/ipX9OIzGl
 P8kEvhZf6WrsMvweh0kqjbkd+6A+45RD/r7Vv//0sDzHl0ZDH5ltOFnxXC8s7scw
 pUqPICycT7whcqWaCUu1kE6l7NJOHg8PQEz0Bm5ZbW8z3nlfvPDkyp8Y1NjiuIb7
 5kfrdxqA5gqhnw==
 =0w/x
 -----END PGP SIGNATURE-----

Merge tag 'x86-apic-2021-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 apic update from Thomas Gleixner:
 "A single commit to make the vector allocation code more resilent
  against an accidental allocation attempt for IRQ2"

* tag 'x86-apic-2021-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/vector: Add a sanity check to prevent IRQ2 allocations
This commit is contained in:
Linus Torvalds 2021-04-26 10:00:38 -07:00
commit 6f78c2a7b7
1 changed files with 13 additions and 0 deletions

View File

@ -543,6 +543,14 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
return -ENOSYS; return -ENOSYS;
/*
* Catch any attempt to touch the cascade interrupt on a PIC
* equipped system.
*/
if (WARN_ON_ONCE(info->flags & X86_IRQ_ALLOC_LEGACY &&
virq == PIC_CASCADE_IR))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) { for (i = 0; i < nr_irqs; i++) {
irqd = irq_domain_get_irq_data(domain, virq + i); irqd = irq_domain_get_irq_data(domain, virq + i);
BUG_ON(!irqd); BUG_ON(!irqd);
@ -745,6 +753,11 @@ void __init lapic_assign_system_vectors(void)
/* Mark the preallocated legacy interrupts */ /* Mark the preallocated legacy interrupts */
for (i = 0; i < nr_legacy_irqs(); i++) { for (i = 0; i < nr_legacy_irqs(); i++) {
/*
* Don't touch the cascade interrupt. It's unusable
* on PIC equipped machines. See the large comment
* in the IO/APIC code.
*/
if (i != PIC_CASCADE_IR) if (i != PIC_CASCADE_IR)
irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
} }