mirror of https://gitee.com/openkylin/linux.git
ARM: SoC cleanups for v4.8
The cleanup branch keeps going down in size as we've completed a lot of the major legacy platform removals and conversions. A handful of changes this time around, some of the themes or larger sets are: - A bunch of i.MX cleanups around platform detection, init call cleanups - Misc fixes of missing/implicit includes - Removal of ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXnnwFAAoJEIwa5zzehBx3zXQP/2a/+XkiseeGkEoiX/6FOfhH XTzipye0OYdEe3kVWFL1sVVXRH6a5sbDJRNtfsQc+KdSG5i7LMHWARRJmIx9CTMB oQ9pEbYKSyBQDHBSOZYT6W+qYOI2SdTYqesjd3yn+FY4SIFBpQ/V3axHnMICIRm9 PmHF1QUQEdtQ2Y9+E1vA1mHcPN9enjlesD3VdRbxVPX/PZw63kx9y8ICVq5I/PX9 DfJRcA+PKIYQghhEZ0cx2bEoKozv7W088C7DD1Umw1NN18pMuvvNQGhid80xUqKY 4bmLSGWqwmSzv1WZ/u1pUnBGGQE9YY1U2b8kZy8hSVg9rupxS8Ang0ztZRRE6nk2 4t8GmWuLDH+7PxFv/skzi1AMAx+4KxSfp3N5qyKr8ddmnYrFWmBPj2AeBqrlziw6 8Z41LQULmf/Gs6McikGUP7ryqd15gNtTJO1wlavqFrPe0fyzcHsgqpIy3YCqZiSE wQ4Hc036xqGknmg6GjHWp+W1rHZVGsnXmvnp1IVRoAGqwBqxNi4ItIXE7an8144H NnWFmPRSsGg26MfEJVsbtPQWNtEGqM2lgr6zn9xirC0cVbQ4ZDtWp2q0bJ1v/cLQ sW6Gu6jgVN8YUPp56lBaXJ5RxHE9V1Sqi4/+KghBKWW0X/BIo99b6PVr2bJRrkaq ZvpvsgzbCHdGqTptF9Dw =SfR/ -----END PGP SIGNATURE----- Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "The cleanup branch keeps going down in size as we've completed a lot of the major legacy platform removals and conversions. A handful of changes this time around, some of the themes or larger sets are: - A bunch of i.MX cleanups around platform detection, init call cleanups - Misc fixes of missing/implicit includes - Removal of ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (40 commits) ARM: mps2: fix typo ARM: s3c64xx: avoid warning about 'struct device_node' bus: mvebu-mbus: make mvebu_mbus_syscore_ops static bus: mvebu-mbus: fix __iomem on register pointers ARM: tegra: Remove board_init_funcs array ARM: iop: Fix indentation ARM: imx: remove cpu_is_mx*() ARM: imx: remove last call to cpu_is_mx5* ARM: imx: rework mx27_pm_init() call ARM: imx: deconstruct mx3_idle ARM: imx: deconstruct mxc_rnga initialization ARM: imx: remove cpu_is_mx1 check ARM: i.MX: Do not explicitly call l2x0_of_init() ARM: i.MX: system.c: Tweak prefetch settings for performance ARM: i.MX: system.c: Replace magic numbers ARM: i.MX: system.c: Remove redundant errata 752271 code ARM: i.MX: system.c: Convert goto to if statement ARM: Kirkwood: fix kirkwood_pm_init() declaration/type ARM: Kirkwood: make kirkwood_disable_mbus_error_propagation() static ARM: orion5x: make orion5x_legacy_handle_irq static ...
This commit is contained in:
Linus Torvalds
commit
6f888fe31d
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@ -327,7 +327,6 @@ choice
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config ARCH_MULTIPLATFORM
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bool "Allow multiple platforms to be selected"
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depends on MMU
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_HAS_SG_CHAIN
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select ARM_PATCH_PHYS_VIRT
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select AUTO_ZRELADDR
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@ -342,7 +341,6 @@ config ARCH_MULTIPLATFORM
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config ARM_SINGLE_ARMV7M
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bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
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depends on !MMU
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_NVIC
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select AUTO_ZRELADDR
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select CLKSRC_OF
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@ -356,12 +354,12 @@ config ARM_SINGLE_ARMV7M
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config ARCH_CLPS711X
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bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
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select ARCH_REQUIRE_GPIOLIB
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select AUTO_ZRELADDR
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select COMMON_CLK
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select CPU_ARM720T
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select GENERIC_CLOCKEVENTS
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select CLPS711X_TIMER
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select GPIOLIB
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select MFD_SYSCON
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select SOC_BUS
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help
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@ -369,10 +367,10 @@ config ARCH_CLPS711X
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config ARCH_GEMINI
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bool "Cortina Systems Gemini"
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select ARCH_REQUIRE_GPIOLIB
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select CLKSRC_MMIO
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select CPU_FA526
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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help
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Support for the Cortina Systems Gemini family SoCs
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@ -393,7 +391,6 @@ config ARCH_EBSA110
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config ARCH_EP93XX
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bool "EP93xx-based"
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select ARM_PATCH_PHYS_VIRT
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select ARM_VIC
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@ -402,6 +399,7 @@ config ARCH_EP93XX
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select CLKSRC_MMIO
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select CPU_ARM920T
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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help
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This enables support for the Cirrus EP93xx series of CPUs.
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@ -442,9 +440,9 @@ config ARCH_IOP13XX
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config ARCH_IOP32X
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bool "IOP32x-based"
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depends on MMU
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select ARCH_REQUIRE_GPIOLIB
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select CPU_XSCALE
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select GPIO_IOP
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select GPIOLIB
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select NEED_RET_TO_USER
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select PCI
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select PLAT_IOP
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@ -455,9 +453,9 @@ config ARCH_IOP32X
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config ARCH_IOP33X
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bool "IOP33x-based"
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depends on MMU
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select ARCH_REQUIRE_GPIOLIB
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select CPU_XSCALE
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select GPIO_IOP
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select GPIOLIB
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select NEED_RET_TO_USER
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select PCI
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select PLAT_IOP
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@ -468,12 +466,12 @@ config ARCH_IXP4XX
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bool "IXP4xx-based"
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depends on MMU
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select ARCH_HAS_DMA_SET_COHERENT_MASK
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_SUPPORTS_BIG_ENDIAN
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select CLKSRC_MMIO
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select CPU_XSCALE
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select DMABOUNCE if PCI
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select MIGHT_HAVE_PCI
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select NEED_MACH_IO_H
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select USB_EHCI_BIG_ENDIAN_DESC
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@ -483,9 +481,9 @@ config ARCH_IXP4XX
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config ARCH_DOVE
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bool "Marvell Dove"
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select ARCH_REQUIRE_GPIOLIB
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select CPU_PJ4
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select MIGHT_HAVE_PCI
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select MULTI_IRQ_HANDLER
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select MVEBU_MBUS
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@ -499,10 +497,10 @@ config ARCH_DOVE
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config ARCH_KS8695
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bool "Micrel/Kendin KS8695"
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select ARCH_REQUIRE_GPIOLIB
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select CLKSRC_MMIO
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select CPU_ARM922T
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select NEED_MACH_MEMORY_H
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help
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Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
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@ -510,11 +508,11 @@ config ARCH_KS8695
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config ARCH_W90X900
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bool "Nuvoton W90X900 CPU"
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CPU_ARM926T
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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help
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Support for Nuvoton (Winbond logic dept.) ARM9 processor,
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At present, the w90x900 has been renamed nuc900, regarding
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@ -526,13 +524,13 @@ config ARCH_W90X900
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config ARCH_LPC32XX
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bool "NXP LPC32XX"
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select CLKDEV_LOOKUP
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select CLKSRC_LPC32XX
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select COMMON_CLK
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select CPU_ARM926T
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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select USE_OF
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@ -543,7 +541,6 @@ config ARCH_PXA
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bool "PXA2xx/PXA3xx-based"
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depends on MMU
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select ARCH_MTD_XIP
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select ARCH_REQUIRE_GPIOLIB
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select ARM_CPU_SUSPEND if PM
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select AUTO_ZRELADDR
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select COMMON_CLK
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@ -554,6 +551,7 @@ config ARCH_PXA
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select CPU_XSCALE if !CPU_XSC3
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select GPIOLIB
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select HAVE_IDE
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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@ -584,7 +582,6 @@ config ARCH_RPC
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config ARCH_SA1100
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bool "SA1100-based"
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select ARCH_MTD_XIP
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_SPARSEMEM_ENABLE
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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@ -593,6 +590,7 @@ config ARCH_SA1100
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select CPU_FREQ
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select CPU_SA1100
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select HAVE_IDE
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select IRQ_DOMAIN
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select ISA
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@ -604,12 +602,12 @@ config ARCH_SA1100
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config ARCH_S3C24XX
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bool "Samsung S3C24XX SoCs"
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select ARCH_REQUIRE_GPIOLIB
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select ATAGS
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select CLKDEV_LOOKUP
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select CLKSRC_SAMSUNG_PWM
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select GPIOLIB
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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@ -625,12 +623,12 @@ config ARCH_S3C24XX
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config ARCH_DAVINCI
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bool "TI DaVinci"
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CPU_ARM926T
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select GENERIC_ALLOCATOR
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select HAVE_IDE
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select USE_OF
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select ZONE_DMA
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@ -642,11 +640,11 @@ config ARCH_OMAP1
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depends on MMU
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_OMAP
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select HAVE_IDE
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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@ -868,7 +866,7 @@ source "arch/arm/mach-zynq/Kconfig"
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config ARCH_EFM32
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bool "Energy Micro efm32"
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depends on ARM_SINGLE_ARMV7M
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select ARCH_REQUIRE_GPIOLIB
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select GPIOLIB
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help
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Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
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processors.
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@ -901,7 +899,7 @@ config MACH_STM32F429
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default y
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config ARCH_MPS2
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bool "ARM MPS2 paltform"
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bool "ARM MPS2 platform"
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depends on ARM_SINGLE_ARMV7M
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select ARM_AMBA
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select CLKSRC_MPS2
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@ -1,8 +1,8 @@
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menuconfig ARCH_AT91
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bool "Atmel SoCs"
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depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select COMMON_CLK_AT91
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select GPIOLIB
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select PINCTRL
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select SOC_BUS
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|
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@ -17,7 +17,7 @@ config ARCH_BCM_IPROC
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select ARM_GLOBAL_TIMER
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select COMMON_CLK_IPROC
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select CLKSRC_MMIO
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select ARCH_REQUIRE_GPIOLIB
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select GPIOLIB
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select ARM_AMBA
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select PINCTRL
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help
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|
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@ -80,7 +80,7 @@ comment "KONA architected SoCs"
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config ARCH_BCM_MOBILE
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bool
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select ARCH_REQUIRE_GPIOLIB
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select GPIOLIB
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select ARM_GIC
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|
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@ -138,7 +138,7 @@ comment "Other Architectures"
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select GPIOLIB
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select ARM_AMBA
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select ARM_ERRATA_411920 if ARCH_MULTI_V6
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select ARM_TIMER_SP804
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|
|
@ -178,7 +178,6 @@ config ARCH_BRCMSTB
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|||
select BRCMSTB_L2_IRQ
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select BCM7120_L2_IRQ
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select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
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||||
select ARCH_WANT_OPTIONAL_GPIOLIB
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||||
select SOC_BRCMSTB
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||||
select SOC_BUS
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||||
help
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@ menuconfig ARCH_BERLIN
|
|||
bool "Marvell Berlin SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_GIC
|
||||
select DW_APB_ICTL
|
||||
select DW_APB_TIMER_OF
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select MFD_SYSCON
|
||||
select PINCTRL
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
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|||
config ARCH_DIGICOLOR
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||||
bool "Conexant Digicolor SoC Support"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKSRC_MMIO
|
||||
select DIGICOLOR_TIMER
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select MFD_SYSCON
|
||||
select PINCTRL
|
||||
select PINCTRL_DIGICOLOR
|
||||
|
|
|
|||
|
|
@ -12,13 +12,13 @@ menuconfig ARCH_EXYNOS
|
|||
depends on ARCH_MULTI_V7
|
||||
select ARCH_HAS_BANDGAP
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select COMMON_CLK_SAMSUNG
|
||||
select EXYNOS_THERMAL
|
||||
select EXYNOS_PMU
|
||||
select EXYNOS_SROM
|
||||
select GPIOLIB
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
menuconfig ARCH_MXC
|
||||
bool "Freescale i.MX family"
|
||||
depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select CLKSRC_IMX_GPT
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
select PM_OPP if PM
|
||||
select SOC_BUS
|
||||
|
|
@ -44,9 +44,6 @@ config MXC_USE_EPIT
|
|||
uses the same clocks as the GPT. Anyway, on some systems the GPT
|
||||
may be in use for other purposes.
|
||||
|
||||
config ARCH_HAS_RNGA
|
||||
bool
|
||||
|
||||
config HAVE_IMX_ANATOP
|
||||
bool
|
||||
|
||||
|
|
@ -90,7 +87,6 @@ config SOC_IMX27
|
|||
config SOC_IMX31
|
||||
bool
|
||||
select CPU_V6
|
||||
select IMX_HAVE_PLATFORM_MXC_RNGA
|
||||
select MXC_AVIC
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
|
|||
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o
|
||||
|
||||
imx5-pm-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@ void imx27_init_early(void);
|
|||
void imx31_init_early(void);
|
||||
void imx35_init_early(void);
|
||||
void mxc_init_irq(void __iomem *);
|
||||
void tzic_init_irq(void);
|
||||
void mx1_init_irq(void);
|
||||
void mx21_init_irq(void);
|
||||
void mx27_init_irq(void);
|
||||
|
|
@ -55,6 +54,7 @@ struct platform_device *mxc_register_gpio(char *name, int id,
|
|||
void mxc_set_cpu_type(unsigned int type);
|
||||
void mxc_restart(enum reboot_mode, const char *);
|
||||
void mxc_arch_reset_init(void __iomem *);
|
||||
void imx1_reset_init(void __iomem *);
|
||||
void imx_set_aips(void __iomem *);
|
||||
void imx_aips_allow_unprivileged_access(const char *compat);
|
||||
int mxc_device_init(void);
|
||||
|
|
@ -67,6 +67,7 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off);
|
|||
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
|
||||
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
|
||||
void imx25_pm_init(void);
|
||||
void imx27_pm_init(void);
|
||||
|
||||
enum mxc_cpu_pwr_mode {
|
||||
WAIT_CLOCKED, /* wfi only */
|
||||
|
|
|
|||
|
|
@ -60,13 +60,9 @@ static int get_mx51_srev(void)
|
|||
/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx51
|
||||
*/
|
||||
int mx51_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx51())
|
||||
return -EINVAL;
|
||||
|
||||
if (mx5_cpu_rev == -1)
|
||||
mx5_cpu_rev = get_mx51_srev();
|
||||
|
||||
|
|
@ -112,13 +108,9 @@ static int get_mx53_srev(void)
|
|||
/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx53
|
||||
*/
|
||||
int mx53_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx53())
|
||||
return -EINVAL;
|
||||
|
||||
if (mx5_cpu_rev == -1)
|
||||
mx5_cpu_rev = get_mx53_srev();
|
||||
|
||||
|
|
|
|||
|
|
@ -10,8 +10,6 @@
|
|||
#include "common.h"
|
||||
|
||||
unsigned int __mxc_cpu_type;
|
||||
EXPORT_SYMBOL(__mxc_cpu_type);
|
||||
|
||||
static unsigned int imx_soc_revision;
|
||||
|
||||
void mxc_set_cpu_type(unsigned int type)
|
||||
|
|
|
|||
|
|
@ -57,10 +57,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
|
|||
config IMX_HAVE_PLATFORM_MXC_NAND
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_MXC_RNGA
|
||||
bool
|
||||
select ARCH_HAS_RNGA
|
||||
|
||||
config IMX_HAVE_PLATFORM_MXC_RTC
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -1,53 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
struct imx_mxc_rnga_data {
|
||||
resource_size_t iobase;
|
||||
};
|
||||
|
||||
#define imx_mxc_rnga_data_entry_single(soc) \
|
||||
{ \
|
||||
.iobase = soc ## _RNGA_BASE_ADDR, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX31
|
||||
static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
|
||||
imx_mxc_rnga_data_entry_single(MX31);
|
||||
#endif /* ifdef CONFIG_SOC_IMX31 */
|
||||
|
||||
static struct platform_device *__init imx_add_mxc_rnga(
|
||||
const struct imx_mxc_rnga_data *data)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
return imx_add_platform_device("mxc_rnga", -1,
|
||||
res, ARRAY_SIZE(res), NULL, 0);
|
||||
}
|
||||
|
||||
static int __init imxXX_add_mxc_rnga(void)
|
||||
{
|
||||
struct platform_device *ret;
|
||||
|
||||
#if defined(CONFIG_SOC_IMX31)
|
||||
if (cpu_is_mx31())
|
||||
ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
|
||||
else
|
||||
#endif /* if defined(CONFIG_SOC_IMX31) */
|
||||
ret = ERR_PTR(-ENODEV);
|
||||
|
||||
return PTR_ERR_OR_ZERO(ret);
|
||||
}
|
||||
arch_initcall(imxXX_add_mxc_rnga);
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
|
||||
*
|
||||
* Based on board-pcm038.h which is :
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_EUKREA_BASEBOARDS_H__
|
||||
#define __MACH_EUKREA_BASEBOARDS_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* This CPU module needs a baseboard to work. After basic initializing
|
||||
* its own devices, it calls baseboard's init function.
|
||||
* TODO: Add your own baseboard init function and call it from
|
||||
* inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
|
||||
*
|
||||
* This example here is for the development board. Refer
|
||||
* mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
|
||||
* mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
|
||||
*/
|
||||
|
||||
extern void eukrea_mbimxsd25_baseboard_init(void);
|
||||
extern void eukrea_mbimxsd35_baseboard_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_EUKREA_BASEBOARDS_H__ */
|
||||
|
|
@ -27,5 +27,6 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
|
|||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
.init_irq = mx27_init_irq,
|
||||
.init_late = imx27_pm_init,
|
||||
.dt_compat = imx27_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -28,10 +28,22 @@ static void __init imx31_dt_timer_init(void)
|
|||
mx31_clocks_init_dt();
|
||||
}
|
||||
|
||||
/* FIXME: replace with DT binding */
|
||||
static const struct resource imx31_rnga_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
static void __init imx31_dt_mach_init(void)
|
||||
{
|
||||
platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
|
||||
ARRAY_SIZE(imx31_rnga_res));
|
||||
}
|
||||
|
||||
DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
|
||||
.map_io = mx31_map_io,
|
||||
.init_early = imx31_init_early,
|
||||
.init_irq = mx31_init_irq,
|
||||
.init_time = imx31_dt_timer_init,
|
||||
.init_machine = imx31_dt_mach_init,
|
||||
.dt_compat = imx31_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -20,20 +20,16 @@
|
|||
#include "common.h"
|
||||
#include "mx35.h"
|
||||
|
||||
static void __init imx35_irq_init(void)
|
||||
{
|
||||
imx_init_l2cache();
|
||||
mx35_init_irq();
|
||||
}
|
||||
|
||||
static const char * const imx35_dt_board_compat[] __initconst = {
|
||||
"fsl,imx35",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.map_io = mx35_map_io,
|
||||
.init_early = imx35_init_early,
|
||||
.init_irq = imx35_irq_init,
|
||||
.init_irq = mx35_init_irq,
|
||||
.dt_compat = imx35_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -22,6 +22,5 @@ static const char * const imx50_dt_board_compat[] __initconst = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
|
||||
.init_irq = tzic_init_irq,
|
||||
.dt_compat = imx50_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -67,7 +67,6 @@ static const char * const imx51_dt_board_compat[] __initconst = {
|
|||
|
||||
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = tzic_init_irq,
|
||||
.init_machine = imx51_dt_init,
|
||||
.init_late = imx51_init_late,
|
||||
.dt_compat = imx51_dt_board_compat,
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ static const char * const imx53_dt_board_compat[] __initconst = {
|
|||
|
||||
DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
|
||||
.init_early = imx53_init_early,
|
||||
.init_irq = tzic_init_irq,
|
||||
.init_machine = imx53_dt_init,
|
||||
.init_late = imx53_init_late,
|
||||
.dt_compat = imx53_dt_board_compat,
|
||||
|
|
|
|||
|
|
@ -407,6 +407,8 @@ static const char * const imx6q_dt_compat[] __initconst = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.smp = smp_ops(imx_smp_ops),
|
||||
.map_io = imx6q_map_io,
|
||||
.init_irq = imx6q_init_irq,
|
||||
|
|
|
|||
|
|
@ -75,6 +75,8 @@ static const char * const imx6sl_dt_compat[] __initconst = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_irq = imx6sl_init_irq,
|
||||
.init_machine = imx6sl_init_machine,
|
||||
.init_late = imx6sl_init_late,
|
||||
|
|
|
|||
|
|
@ -103,6 +103,8 @@ static const char * const imx6sx_dt_compat[] __initconst = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_irq = imx6sx_init_irq,
|
||||
.init_machine = imx6sx_init_machine,
|
||||
.dt_compat = imx6sx_dt_compat,
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ void __init mx1_init_irq(void)
|
|||
|
||||
void __init imx1_soc_init(void)
|
||||
{
|
||||
mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
|
||||
imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
|
||||
mxc_device_init();
|
||||
|
||||
mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
|
||||
|
|
|
|||
|
|
@ -98,4 +98,6 @@ void __init imx27_soc_init(void)
|
|||
/* imx27 has the imx21 type audmux */
|
||||
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
|
||||
ARRAY_SIZE(imx27_audmux_res));
|
||||
|
||||
imx27_pm_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
|
|
@ -38,8 +39,6 @@ static void imx3_idle(void)
|
|||
{
|
||||
unsigned long reg = 0;
|
||||
|
||||
mx3_cpu_lp_set(MX3_WAIT);
|
||||
|
||||
__asm__ __volatile__(
|
||||
/* disable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
|
|
@ -135,11 +134,20 @@ void __init mx31_map_io(void)
|
|||
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
|
||||
}
|
||||
|
||||
static void imx31_idle(void)
|
||||
{
|
||||
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
|
||||
reg &= ~MXC_CCM_CCMR_LPM_MASK;
|
||||
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
|
||||
|
||||
imx3_idle();
|
||||
}
|
||||
|
||||
void __init imx31_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX31);
|
||||
arch_ioremap_caller = imx3_ioremap_caller;
|
||||
arm_pm_idle = imx3_idle;
|
||||
arm_pm_idle = imx31_idle;
|
||||
mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
|
||||
}
|
||||
|
||||
|
|
@ -167,6 +175,10 @@ static const struct resource imx31_audmux_res[] __initconst = {
|
|||
DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
static const struct resource imx31_rnga_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
void __init imx31_soc_init(void)
|
||||
{
|
||||
int to_version = mx31_revision() >> 4;
|
||||
|
|
@ -195,6 +207,8 @@ void __init imx31_soc_init(void)
|
|||
|
||||
platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
|
||||
ARRAY_SIZE(imx31_audmux_res));
|
||||
platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
|
||||
ARRAY_SIZE(imx31_rnga_res));
|
||||
}
|
||||
#endif /* ifdef CONFIG_SOC_IMX31 */
|
||||
|
||||
|
|
@ -212,11 +226,21 @@ void __init mx35_map_io(void)
|
|||
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
|
||||
}
|
||||
|
||||
static void imx35_idle(void)
|
||||
{
|
||||
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
|
||||
reg &= ~MXC_CCM_CCMR_LPM_MASK;
|
||||
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
|
||||
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
|
||||
|
||||
imx3_idle();
|
||||
}
|
||||
|
||||
void __init imx35_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX35);
|
||||
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
|
||||
arm_pm_idle = imx3_idle;
|
||||
arm_pm_idle = imx35_idle;
|
||||
arch_ioremap_caller = imx3_ioremap_caller;
|
||||
mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -45,105 +45,7 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned int __mxc_cpu_type;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX1
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX1
|
||||
# endif
|
||||
# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
|
||||
#else
|
||||
# define cpu_is_mx1() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX21
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX21
|
||||
# endif
|
||||
# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
|
||||
#else
|
||||
# define cpu_is_mx21() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX25
|
||||
# endif
|
||||
# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
|
||||
#else
|
||||
# define cpu_is_mx25() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX27
|
||||
# endif
|
||||
# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
|
||||
#else
|
||||
# define cpu_is_mx27() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX31
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX31
|
||||
# endif
|
||||
# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
|
||||
#else
|
||||
# define cpu_is_mx31() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX35
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX35
|
||||
# endif
|
||||
# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
|
||||
#else
|
||||
# define cpu_is_mx35() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX51
|
||||
# endif
|
||||
# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
|
||||
#else
|
||||
# define cpu_is_mx51() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX53
|
||||
# endif
|
||||
# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
|
||||
#else
|
||||
# define cpu_is_mx53() (0)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_SOC_IMX6SL
|
||||
static inline bool cpu_is_imx6sl(void)
|
||||
{
|
||||
|
|
@ -190,9 +92,6 @@ int tzic_enable_wake(void);
|
|||
extern struct cpu_op *(*get_cpu_op)(int *op);
|
||||
#endif
|
||||
|
||||
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
|
||||
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
|
||||
|
||||
#define imx_readl readl_relaxed
|
||||
#define imx_readw readw_relaxed
|
||||
#define imx_writel writel_relaxed
|
||||
|
|
|
|||
|
|
@ -37,13 +37,7 @@ static const struct platform_suspend_ops mx27_suspend_ops = {
|
|||
.valid = suspend_valid_only_mem,
|
||||
};
|
||||
|
||||
static int __init mx27_pm_init(void)
|
||||
void __init imx27_pm_init(void)
|
||||
{
|
||||
if (!cpu_is_mx27())
|
||||
return 0;
|
||||
|
||||
suspend_set_ops(&mx27_suspend_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(mx27_pm_init);
|
||||
|
|
|
|||
|
|
@ -1,38 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "crmregs-imx3.h"
|
||||
#include "devices/devices-common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
/*
|
||||
* Set cpu low power mode before WFI instruction. This function is called
|
||||
* mx3 because it can be used for mx31 and mx35.
|
||||
* Currently only WAIT_MODE is supported.
|
||||
*/
|
||||
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
|
||||
{
|
||||
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
|
||||
reg &= ~MXC_CCM_CCMR_LPM_MASK;
|
||||
|
||||
switch (mode) {
|
||||
case MX3_WAIT:
|
||||
if (cpu_is_mx35())
|
||||
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
|
||||
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
|
||||
break;
|
||||
default:
|
||||
pr_err("Unknown cpu power mode: %d\n", mode);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -34,25 +34,19 @@
|
|||
|
||||
static void __iomem *wdog_base;
|
||||
static struct clk *wdog_clk;
|
||||
static int wcr_enable = (1 << 2);
|
||||
|
||||
/*
|
||||
* Reset the system. It is called by machine_restart().
|
||||
*/
|
||||
void mxc_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
unsigned int wcr_enable;
|
||||
|
||||
if (!wdog_base)
|
||||
goto reset_fallback;
|
||||
|
||||
if (!IS_ERR(wdog_clk))
|
||||
clk_enable(wdog_clk);
|
||||
|
||||
if (cpu_is_mx1())
|
||||
wcr_enable = (1 << 0);
|
||||
else
|
||||
wcr_enable = (1 << 2);
|
||||
|
||||
/* Assert SRS signal */
|
||||
imx_writew(wcr_enable, wdog_base);
|
||||
/*
|
||||
|
|
@ -89,6 +83,14 @@ void __init mxc_arch_reset_init(void __iomem *base)
|
|||
clk_prepare(wdog_clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX1
|
||||
void __init imx1_reset_init(void __iomem *base)
|
||||
{
|
||||
wcr_enable = (1 << 0);
|
||||
mxc_arch_reset_init(base);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
void __init imx_init_l2cache(void)
|
||||
{
|
||||
|
|
@ -98,38 +100,28 @@ void __init imx_init_l2cache(void)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
|
||||
if (!np)
|
||||
goto out;
|
||||
return;
|
||||
|
||||
l2x0_base = of_iomap(np, 0);
|
||||
if (!l2x0_base) {
|
||||
of_node_put(np);
|
||||
goto out;
|
||||
if (!l2x0_base)
|
||||
goto put_node;
|
||||
|
||||
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
|
||||
/* Configure the L2 PREFETCH and POWER registers */
|
||||
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
|
||||
val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
|
||||
L310_PREFETCH_CTRL_INSTR_PREFETCH |
|
||||
L310_PREFETCH_CTRL_DATA_PREFETCH;
|
||||
|
||||
/* Set perfetch offset to improve performance */
|
||||
val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
|
||||
val |= 15;
|
||||
|
||||
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
|
||||
}
|
||||
|
||||
if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
|
||||
goto skip_if_enabled;
|
||||
|
||||
/* Configure the L2 PREFETCH and POWER registers */
|
||||
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
|
||||
val |= 0x70800000;
|
||||
/*
|
||||
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
|
||||
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
|
||||
* But according to ARM PL310 errata: 752271
|
||||
* ID: 752271: Double linefill feature can cause data corruption
|
||||
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
|
||||
* Workaround: The only workaround to this erratum is to disable the
|
||||
* double linefill feature. This is the default behavior.
|
||||
*/
|
||||
if (cpu_is_imx6q())
|
||||
val &= ~(1 << 30 | 1 << 23);
|
||||
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
|
||||
|
||||
skip_if_enabled:
|
||||
iounmap(l2x0_base);
|
||||
put_node:
|
||||
of_node_put(np);
|
||||
|
||||
out:
|
||||
l2x0_of_init(0, ~0);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,12 +9,11 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
@ -153,13 +152,11 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
|
|||
* interrupts. It registers the interrupt enable and disable functions
|
||||
* to the kernel for each interrupt source.
|
||||
*/
|
||||
void __init tzic_init_irq(void)
|
||||
static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
|
||||
{
|
||||
struct device_node *np;
|
||||
int irq_base;
|
||||
int i;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
|
||||
tzic_base = of_iomap(np, 0);
|
||||
WARN_ON(!tzic_base);
|
||||
|
||||
|
|
@ -199,7 +196,10 @@ void __init tzic_init_irq(void)
|
|||
#endif
|
||||
|
||||
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
|
||||
|
||||
/**
|
||||
* tzic_enable_wake() - enable wakeup interrupt
|
||||
|
|
|
|||
|
|
@ -32,9 +32,9 @@ config ARCH_INTEGRATOR_AP
|
|||
config INTEGRATOR_IMPD1
|
||||
bool "Include support for Integrator/IM-PD1"
|
||||
depends on ARCH_INTEGRATOR_AP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_VIC
|
||||
select GPIO_PL061 if GPIOLIB
|
||||
select GPIO_PL061
|
||||
select GPIOLIB
|
||||
help
|
||||
The IM-PD1 is an add-on logic module for the Integrator which
|
||||
allows ARM(R) Ltd PrimeCells to be developed and evaluated.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
menuconfig ARCH_MESON
|
||||
bool "Amlogic Meson SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select GENERIC_IRQ_CHIP
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
menuconfig ARCH_MMP
|
||||
bool "Marvell PXA168/910/MMP2"
|
||||
depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_PXA
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
select PLAT_PXA
|
||||
help
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ menuconfig ARCH_MOXART
|
|||
select ARM_DMA_MEM_BUFFERABLE
|
||||
select MOXART_TIMER
|
||||
select GENERIC_IRQ_CHIP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select PHYLIB if NETDEVICES
|
||||
help
|
||||
Say Y here if you want to run your kernel on hardware with a
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
menuconfig ARCH_MV78XX0
|
||||
bool "Marvell MV78xx0"
|
||||
depends on ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CPU_FEROCEON
|
||||
select GPIOLIB
|
||||
select MVEBU_MBUS
|
||||
select PCI
|
||||
select PLAT_ORION_LEGACY
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ menuconfig ARCH_MVEBU
|
|||
select SOC_BUS
|
||||
select MVEBU_MBUS
|
||||
select ZONE_DMA if ARM_LPAE
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select PCI_QUIRKS if PCI
|
||||
select OF_ADDRESS_PCI
|
||||
|
||||
|
|
@ -119,8 +119,8 @@ config MACH_DOVE
|
|||
config MACH_KIRKWOOD
|
||||
bool "Marvell Kirkwood boards"
|
||||
depends on ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CPU_FEROCEON
|
||||
select GPIOLIB
|
||||
select KIRKWOOD_CLK
|
||||
select MACH_MVEBU_ANY
|
||||
select ORION_IRQCHIP
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#ifndef __MACH_370_XP_COHERENCY_H
|
||||
#define __MACH_370_XP_COHERENCY_H
|
||||
|
||||
extern void __iomem *coherency_base; /* for coherency_ll.S */
|
||||
extern unsigned long coherency_phys_base;
|
||||
int set_cpu_coherent(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/resource.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static void __iomem *cpu_reset_base;
|
||||
static size_t cpu_reset_size;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
#include "kirkwood.h"
|
||||
#include "kirkwood-pm.h"
|
||||
|
||||
static void __iomem *ddr_operation_base;
|
||||
static void __iomem *memory_pm_ctrl;
|
||||
|
|
@ -66,11 +67,10 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = {
|
|||
.valid = kirkwood_pm_valid_standby,
|
||||
};
|
||||
|
||||
int __init kirkwood_pm_init(void)
|
||||
void __init kirkwood_pm_init(void)
|
||||
{
|
||||
ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
|
||||
memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
|
||||
|
||||
suspend_set_ops(&kirkwood_suspend_ops);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static void __init kirkwood_dt_eth_fixup(void)
|
|||
* causes mbus errors (which can occur for example for PCI aborts) to
|
||||
* throw CPU aborts, which we're not set up to deal with.
|
||||
*/
|
||||
void kirkwood_disable_mbus_error_propagation(void)
|
||||
static void kirkwood_disable_mbus_error_propagation(void)
|
||||
{
|
||||
void __iomem *cpu_config;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/suspend.h>
|
||||
|
||||
#include "coherency.h"
|
||||
#include "common.h"
|
||||
#include "pmsu.h"
|
||||
|
||||
#define SDRAM_CONFIG_OFFS 0x0
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/mvebu-pmsu.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -38,7 +39,7 @@
|
|||
#include <asm/suspend.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include "common.h"
|
||||
|
||||
#include "pmsu.h"
|
||||
|
||||
#define PMSU_BASE_OFFSET 0x100
|
||||
#define PMSU_REG_SIZE 0x1000
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_MACH_MVEBU_V7)
|
||||
void mvebu_armada375_smp_wa_init(void)
|
||||
static void mvebu_armada375_smp_wa_init(void)
|
||||
{
|
||||
u32 dev, rev;
|
||||
phys_addr_t resume_addr_reg;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ config SOC_IMX28
|
|||
config ARCH_MXS
|
||||
bool "Freescale MXS (i.MX23, i.MX28) support"
|
||||
depends on ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select MXS_TIMER
|
||||
select PINCTRL
|
||||
select SOC_BUS
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
menuconfig ARCH_NOMADIK
|
||||
bool "ST-Ericsson Nomadik"
|
||||
depends on ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_VIC
|
||||
select CLKSRC_NOMADIK_MTU
|
||||
select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
|
||||
select CPU_ARM926T
|
||||
select GPIOLIB
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select PINCTRL
|
||||
select PINCTRL_NOMADIK
|
||||
|
|
|
|||
|
|
@ -92,9 +92,9 @@ config ARCH_OMAP2PLUS
|
|||
select ARCH_HAS_BANDGAP
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_OMAP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select MACH_OMAP_GENERIC
|
||||
select MEMORY
|
||||
select MFD_SYSCON
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
menuconfig ARCH_ORION5X
|
||||
bool "Marvell Orion"
|
||||
depends on MMU && ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CPU_FEROCEON
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GPIOLIB
|
||||
select MVEBU_MBUS
|
||||
select PCI
|
||||
select PLAT_ORION_LEGACY
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ static int __initdata gpio0_irqs[4] = {
|
|||
IRQ_ORION5X_GPIO_24_31,
|
||||
};
|
||||
|
||||
asmlinkage void
|
||||
static asmlinkage void
|
||||
__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
u32 stat;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
menuconfig ARCH_OXNAS
|
||||
bool "Oxford Semiconductor OXNAS Family SoCs"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
depends on ARCH_MULTI_V5
|
||||
help
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
config ARCH_PICOXCELL
|
||||
bool "Picochip PicoXcell"
|
||||
depends on ARCH_MULTI_V6
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_VIC
|
||||
select DW_APB_TIMER_OF
|
||||
select GPIOLIB
|
||||
select HAVE_TCM
|
||||
select NO_IOPORT_MAP
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ menuconfig ARCH_SIRF
|
|||
depends on ARCH_MULTI_V7
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select RESET_CONTROLLER
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select NO_IOPORT_MAP
|
||||
select REGMAP
|
||||
select PINCTRL
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ config ARCH_ROCKCHIP
|
|||
select PINCTRL
|
||||
select PINCTRL_ROCKCHIP
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select GPIOLIB
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ if ARCH_S3C24XX
|
|||
|
||||
config PLAT_S3C24XX
|
||||
def_bool y
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select NO_IOPORT_MAP
|
||||
select S3C_DEV_NAND
|
||||
select IRQ_DOMAIN
|
||||
|
|
|
|||
|
|
@ -520,7 +520,7 @@
|
|||
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
|
||||
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
|
||||
|
||||
/* interrupt filtering conrrol for EINT16..EINT23 */
|
||||
/* interrupt filtering control for EINT16..EINT23 */
|
||||
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
|
||||
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
|
||||
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@ void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
|
|||
* @timings: The IO timing information to fill out.
|
||||
*
|
||||
* Calculate the @timings timing information from the current frequency
|
||||
* information in @cfg, and the new frequency configur
|
||||
* information in @cfg, and the new frequency configuration
|
||||
* through all the IO banks, reading the state and then updating @iot
|
||||
* as necessary.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -522,7 +522,7 @@ static void __init n30_hwinit(void)
|
|||
*
|
||||
* The pull ups for H6/H7 are enabled on N30 but not on the
|
||||
* N35/PiN. I suppose is useful for a budget model of the N30
|
||||
* with no bluetooh. It doesn't hurt to have the pull ups
|
||||
* with no bluetooth. It doesn't hurt to have the pull ups
|
||||
* enabled on the N35, so leave them enabled for all models.
|
||||
*/
|
||||
__raw_writel(0x0028aaaa, S3C2410_GPHCON);
|
||||
|
|
|
|||
|
|
@ -143,7 +143,7 @@ static int osiris_dvs_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
|
||||
/* the CONFIG_PM block is so small, it isn't worth actually compiling it
|
||||
* out if the configuration isn't set. */
|
||||
|
||||
static int osiris_dvs_suspend(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -32,11 +32,12 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/cpu-freq-core.h>
|
||||
|
||||
/* This array should be sorted in ascending order of the frequencies */
|
||||
static struct cpufreq_frequency_table pll_vals_12MHz[] = {
|
||||
{ .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
|
||||
{ .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
|
||||
{ .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
|
||||
{ .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
|
||||
{ .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
|
||||
{ .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
|
||||
{ .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
|
||||
{ .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/cpu-freq-core.h>
|
||||
|
||||
/* This array should be sorted in ascending order of the frequencies */
|
||||
static struct cpufreq_frequency_table s3c2440_plls_12[] = {
|
||||
{ .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
|
||||
{ .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/cpu-freq-core.h>
|
||||
|
||||
/* This array should be sorted in ascending order of the frequencies */
|
||||
static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
|
||||
{ .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
|
||||
{ .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@
|
|||
menuconfig ARCH_S3C64XX
|
||||
bool "Samsung S3C64XX"
|
||||
depends on ARCH_MULTI_V6
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_VIC
|
||||
select CLKSRC_SAMSUNG_PWM
|
||||
select COMMON_CLK_SAMSUNG
|
||||
select GPIO_SAMSUNG if ATAGS
|
||||
select GPIOLIB
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_TCM
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ void s3c64xx_init_io(struct map_desc *mach_desc, int size);
|
|||
|
||||
void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
struct device_node;
|
||||
void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
||||
unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
|
||||
void s3c64xx_set_xtal_freq(unsigned long freq);
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@
|
|||
|
||||
#define S3C64XX_PA_USB_HSPHY (0x7C100000)
|
||||
|
||||
/* compatibiltiy defines. */
|
||||
/* compatibility defines. */
|
||||
#define S3C_PA_TIMER S3C64XX_PA_TIMER
|
||||
#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
|
||||
#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
|
||||
|
|
|
|||
|
|
@ -11,10 +11,10 @@ config ARCH_S5PV210
|
|||
bool "Samsung S5PV210/S5PC110"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_VIC
|
||||
select CLKSRC_SAMSUNG_PWM
|
||||
select COMMON_CLK_SAMSUNG
|
||||
select GPIOLIB
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ menuconfig ARCH_RENESAS
|
|||
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
|
||||
select NO_IOPORT_MAP
|
||||
select PINCTRL
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select ZONE_DMA if ARM_LPAE
|
||||
|
||||
if ARCH_RENESAS
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@
|
|||
menuconfig PLAT_SPEAR
|
||||
bool "ST SPEAr Family"
|
||||
depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select CLKSRC_MMIO
|
||||
select GPIOLIB
|
||||
|
||||
if PLAT_SPEAR
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ menuconfig ARCH_STI
|
|||
select MFD_SYSCON
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select ARM_ERRATA_775420
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
menuconfig ARCH_SUNXI
|
||||
bool "Allwinner SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
select SUN4I_TIMER
|
||||
select RESET_CONTROLLER
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
menuconfig ARCH_TEGRA
|
||||
bool "NVIDIA Tegra"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select CLKSRC_MMIO
|
||||
select GPIOLIB
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select PINCTRL
|
||||
|
|
|
|||
|
|
@ -1,4 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2011, ARM Ltd.
|
||||
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_COMMON_H
|
||||
#define __MACH_TEGRA_COMMON_H
|
||||
|
||||
extern const struct smp_operations tegra_smp_ops;
|
||||
|
||||
extern int tegra_cpu_kill(unsigned int cpu);
|
||||
extern void tegra_cpu_die(unsigned int cpu);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/suspend.h>
|
||||
#include <asm/psci.h>
|
||||
|
||||
#include "cpuidle.h"
|
||||
#include "pm.h"
|
||||
#include "sleep.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
#include "cpuidle.h"
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "irq.h"
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
#include "cpuidle.h"
|
||||
#include "pm.h"
|
||||
#include "sleep.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -23,8 +23,10 @@ void tegra20_cpuidle_pcie_irqs_in_use(void);
|
|||
int tegra30_cpuidle_init(void);
|
||||
int tegra114_cpuidle_init(void);
|
||||
void tegra_cpuidle_init(void);
|
||||
void tegra_cpuidle_pcie_irqs_in_use(void);
|
||||
#else
|
||||
static inline void tegra_cpuidle_init(void) {}
|
||||
static inline void tegra_cpuidle_pcie_irqs_in_use(void) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "sleep.h"
|
||||
|
||||
static void (*tegra_hotplug_shutdown)(void);
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#include "board.h"
|
||||
#include "iomap.h"
|
||||
#include "irq.h"
|
||||
|
||||
#define SGI_MASK 0xFFFF
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ void tegra30_sleep_core_init(void);
|
|||
|
||||
void tegra_clear_cpu_in_lp2(void);
|
||||
bool tegra_set_cpu_in_lp2(void);
|
||||
|
||||
int tegra_cpu_do_idle(void);
|
||||
void tegra_idle_lp2_last(void);
|
||||
extern void (*tegra_tear_down_cpu)(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -118,32 +118,14 @@ static void __init tegra_dt_init(void)
|
|||
of_platform_default_populate(NULL, NULL, parent);
|
||||
}
|
||||
|
||||
static void __init paz00_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
|
||||
tegra_paz00_wifikill_init();
|
||||
}
|
||||
|
||||
static struct {
|
||||
char *machine;
|
||||
void (*init)(void);
|
||||
} board_init_funcs[] = {
|
||||
{ "compal,paz00", paz00_init },
|
||||
};
|
||||
|
||||
static void __init tegra_dt_init_late(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
tegra_init_suspend();
|
||||
tegra_cpuidle_init();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
|
||||
if (of_machine_is_compatible(board_init_funcs[i].machine)) {
|
||||
board_init_funcs[i].init();
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
|
||||
of_machine_is_compatible("compal,paz00"))
|
||||
tegra_paz00_wifikill_init();
|
||||
}
|
||||
|
||||
static const char * const tegra_dt_board_compat[] = {
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
menuconfig ARCH_U300
|
||||
bool "ST-Ericsson U300 Series"
|
||||
depends on ARCH_MULTI_V5 && MMU
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_VIC
|
||||
select U300_TIMER
|
||||
select CPU_ARM926T
|
||||
select GPIOLIB
|
||||
select HAVE_TCM
|
||||
select PINCTRL
|
||||
select PINCTRL_COH901
|
||||
|
|
|
|||
|
|
@ -101,21 +101,13 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus)
|
|||
np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-smpctrl");
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
of_node_put(np);
|
||||
if (!ret) {
|
||||
rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2;
|
||||
} else {
|
||||
/* try old binding too */
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"socionext,uniphier-system-bus-controller");
|
||||
ret = of_address_to_resource(np, 1, &res);
|
||||
of_node_put(np);
|
||||
if (ret) {
|
||||
pr_err("failed to get resource of SMP control\n");
|
||||
return ret;
|
||||
}
|
||||
rom_rsv2_phys = res.start + 0x1000 + UNIPHIER_SMPCTRL_ROM_RSV2;
|
||||
if (ret) {
|
||||
pr_err("failed to get resource of SMP control\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2;
|
||||
|
||||
ret = uniphier_smp_copy_trampoline(rom_rsv2_phys);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -3,13 +3,13 @@ menuconfig ARCH_U8500
|
|||
depends on ARCH_MULTI_V7 && MMU
|
||||
select AB8500_CORE
|
||||
select ABX500_CORE
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select CLKSRC_NOMADIK_MTU
|
||||
select GPIOLIB
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select PINCTRL
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
menuconfig ARCH_VEXPRESS
|
||||
bool "ARM Ltd. Versatile Express family"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select ARM_GLOBAL_TIMER
|
||||
select ARM_TIMER_SP804
|
||||
select COMMON_CLK_VERSATILE
|
||||
select GPIOLIB
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select HAVE_PATA_PLATFORM
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#include <asm/smp_plat.h>
|
||||
#include <asm/cp15.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
static inline void cpu_enter_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@
|
|||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "spc.h"
|
||||
|
||||
#define SPCLOG "vexpress-spc: "
|
||||
|
||||
#define PERF_LVL_A15 0x00
|
||||
|
|
@ -319,17 +321,15 @@ static int ve_spc_waitforcompletion(int req_type)
|
|||
|
||||
static int ve_spc_set_performance(int cluster, u32 freq)
|
||||
{
|
||||
u32 perf_cfg_reg, perf_stat_reg;
|
||||
u32 perf_cfg_reg;
|
||||
int ret, perf, req_type;
|
||||
|
||||
if (cluster_is_a15(cluster)) {
|
||||
req_type = CA15_DVFS;
|
||||
perf_cfg_reg = PERF_LVL_A15;
|
||||
perf_stat_reg = PERF_REQ_A15;
|
||||
} else {
|
||||
req_type = CA7_DVFS;
|
||||
perf_cfg_reg = PERF_LVL_A7;
|
||||
perf_stat_reg = PERF_REQ_A7;
|
||||
}
|
||||
|
||||
perf = ve_spc_find_performance_index(cluster, freq);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
config ARCH_VT8500
|
||||
bool
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select VT8500_TIMER
|
||||
select PINCTRL
|
||||
|
|
|
|||
|
|
@ -20,12 +20,12 @@
|
|||
* the IOP3xx OCCDR must be mapped uncached and unbuffered.
|
||||
*/
|
||||
static struct map_desc iop3xx_std_desc[] __initdata = {
|
||||
{ /* mem mapped registers */
|
||||
{ /* mem mapped registers */
|
||||
.virtual = IOP3XX_PERIPHERAL_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
|
||||
.length = IOP3XX_PERIPHERAL_SIZE,
|
||||
.type = MT_UNCACHED,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
void __init iop3xx_map_io(void)
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ struct s3c2410_iobank_timing {
|
|||
unsigned int tacs;
|
||||
unsigned int tcos;
|
||||
unsigned int tacc;
|
||||
unsigned int tcoh; /* nCS hold afrer nOE/nWE */
|
||||
unsigned int tcoh; /* nCS hold after nOE/nWE */
|
||||
unsigned int tcah; /* Address hold after nCS */
|
||||
unsigned char nwait_en; /* nWait enabled for bank. */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ struct s3c2410fb_display {
|
|||
|
||||
struct s3c2410fb_mach_info {
|
||||
|
||||
struct s3c2410fb_display *displays; /* attached diplays info */
|
||||
struct s3c2410fb_display *displays; /* attached displays info */
|
||||
unsigned num_displays; /* number of defined displays */
|
||||
unsigned default_display;
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ struct samsung_gpio_chip;
|
|||
* struct samsung_gpio_cfg GPIO configuration
|
||||
* @cfg_eint: Configuration setting when used for external interrupt source
|
||||
* @get_pull: Read the current pull configuration for the GPIO
|
||||
* @set_pull: Set the current pull configuraiton for the GPIO
|
||||
* @set_pull: Set the current pull configuration for the GPIO
|
||||
* @set_config: Set the current configuration for the GPIO
|
||||
* @get_config: Read the current configuration for the GPIO
|
||||
*
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* http://armlinux.simtec.co.uk
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C Power Mangament - suspend/resume memory corruptiuon check.
|
||||
* S3C Power Mangament - suspend/resume memory corruption check.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* Copyright (c) 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
|
||||
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
|
||||
*
|
||||
* Watchdog reset support for Samsung SoCs.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include <plat/platsmp.h>
|
||||
|
||||
/*
|
||||
* Write pen_release in a way that is guaranteed to be visible to all
|
||||
* observers, irrespective of whether they're taking part in coherency
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ struct mvebu_mbus_soc_data {
|
|||
unsigned int (*win_remap_offset)(const int win);
|
||||
void (*setup_cpu_target)(struct mvebu_mbus_state *s);
|
||||
int (*save_cpu_target)(struct mvebu_mbus_state *s,
|
||||
u32 *store_addr);
|
||||
u32 __iomem *store_addr);
|
||||
int (*show_cpu_target)(struct mvebu_mbus_state *s,
|
||||
struct seq_file *seq, void *v);
|
||||
};
|
||||
|
|
@ -728,7 +728,7 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
|
|||
|
||||
static int
|
||||
mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
|
||||
u32 *store_addr)
|
||||
u32 __iomem *store_addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -780,7 +780,7 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
|
|||
|
||||
static int
|
||||
mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
|
||||
u32 *store_addr)
|
||||
u32 __iomem *store_addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -796,7 +796,7 @@ mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
|
|||
return 4;
|
||||
}
|
||||
|
||||
int mvebu_mbus_save_cpu_target(u32 *store_addr)
|
||||
int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
|
||||
{
|
||||
return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
|
||||
}
|
||||
|
|
@ -1089,7 +1089,7 @@ static void mvebu_mbus_resume(void)
|
|||
}
|
||||
}
|
||||
|
||||
struct syscore_ops mvebu_mbus_syscore_ops = {
|
||||
static struct syscore_ops mvebu_mbus_syscore_ops = {
|
||||
.suspend = mvebu_mbus_suspend,
|
||||
.resume = mvebu_mbus_resume,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@ static ssize_t vexpress_reset_active_store(struct device *dev,
|
|||
return err ? err : count;
|
||||
}
|
||||
|
||||
DEVICE_ATTR(active, S_IRUGO | S_IWUSR, vexpress_reset_active_show,
|
||||
vexpress_reset_active_store);
|
||||
static DEVICE_ATTR(active, S_IRUGO | S_IWUSR, vexpress_reset_active_show,
|
||||
vexpress_reset_active_store);
|
||||
|
||||
|
||||
enum vexpress_reset_func { FUNC_RESET, FUNC_SHUTDOWN, FUNC_REBOOT };
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(vo
|
|||
}
|
||||
#endif
|
||||
|
||||
int mvebu_mbus_save_cpu_target(u32 *store_addr);
|
||||
int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
|
||||
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
|
||||
void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
|
||||
int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
|
||||
|
|
|
|||
Loading…
Reference in New Issue