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sh: Kill off dead UBC headers. 

Nothing is using these now, so kill them all off.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2010-01-05 19:16:35 +09:00
parent 4352fc1b12
commit 7025bec912
6 changed files with 8 additions and 221 deletions
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70
arch/sh/include/asm/ubc.h
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@ -1,70 +0,0 @@
/*
* include/asm-sh/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_UBC_H
#define __ASM_SH_UBC_H
#ifdef __KERNEL__
#include <cpu/ubc.h>
/* User Break Controller */
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
#else
#define UBC_TYPE_SH7729 0
#endif
#define BAMR_ASID (1 << 2)
#define BAMR_NONE 0
#define BAMR_10 0x1
#define BAMR_12 0x2
#define BAMR_ALL 0x3
#define BAMR_16 0x8
#define BAMR_20 0x9
#define BBR_INST (1 << 4)
#define BBR_DATA (2 << 4)
#define BBR_READ (1 << 2)
#define BBR_WRITE (2 << 2)
#define BBR_BYTE 0x1
#define BBR_HALF 0x2
#define BBR_LONG 0x3
#define BBR_QUAD (1 << 6) /* SH7750 */
#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
#define BRCR_CMFA (1 << 15)
#define BRCR_CMFB (1 << 14)
#if defined CONFIG_CPU_SH2A
#define BRCR_CMFCA (1 << 15)
#define BRCR_CMFCB (1 << 14)
#define BRCR_CMFDA (1 << 13)
#define BRCR_CMFDB (1 << 12)
#define BRCR_PCBB (1 << 6) /* 1: after execution */
#define BRCR_PCBA (1 << 5) /* 1: after execution */
#define BRCR_PCTE 0
#else
#define BRCR_PCTE (1 << 11)
#define BRCR_PCBA (1 << 10) /* 1: after execution */
#define BRCR_DBEB (1 << 7)
#define BRCR_PCBB (1 << 6)
#define BRCR_SEQ (1 << 3)
#define BRCR_UBDE (1 << 0)
#endif
/*
* All SH parts have 2 UBC channels. I defy any hardware designer to
* invalidate this assertion.
*/
#define NR_UBC_CHANNELS 2
#endif /* __KERNEL__ */
#endif /* __ASM_SH_UBC_H */

32
arch/sh/include/cpu-sh2/cpu/ubc.h
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@ -1,32 +0,0 @@
/*
* include/asm-sh/cpu-sh2/ubc.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_UBC_H
#define __ASM_CPU_SH2_UBC_H
#define UBC_BARA 0xffffff40
#define UBC_BAMRA 0xffffff44
#define UBC_BBRA 0xffffff48
#define UBC_BARB 0xffffff60
#define UBC_BAMRB 0xffffff64
#define UBC_BBRB 0xffffff68
#define UBC_BDRB 0xffffff70
#define UBC_BDMRB 0xffffff74
#define UBC_BRCR 0xffffff78
/*
* We don't have any ASID changes to make in the UBC on the SH-2.
*
* Make these purposely invalid to track misuse.
*/
#define UBC_BASRA 0x00000000
#define UBC_BASRB 0x00000000
#endif /* __ASM_CPU_SH2_UBC_H */

42
arch/sh/include/cpu-sh3/cpu/ubc.h
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@ -1,42 +0,0 @@
/*
* include/asm-sh/cpu-sh3/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_UBC_H
#define __ASM_CPU_SH3_UBC_H
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define UBC_BARA 0xa4ffffb0
#define UBC_BAMRA 0xa4ffffb4
#define UBC_BBRA 0xa4ffffb8
#define UBC_BASRA 0xffffffe4
#define UBC_BARB 0xa4ffffa0
#define UBC_BAMRB 0xa4ffffa4
#define UBC_BBRB 0xa4ffffa8
#define UBC_BASRB 0xffffffe8
#define UBC_BDRB 0xa4ffff90
#define UBC_BDMRB 0xa4ffff94
#define UBC_BRCR 0xa4ffff98
#else
#define UBC_BARA 0xffffffb0
#define UBC_BAMRA 0xffffffb4
#define UBC_BBRA 0xffffffb8
#define UBC_BASRA 0xffffffe4
#define UBC_BARB 0xffffffa0
#define UBC_BAMRB 0xffffffa4
#define UBC_BBRB 0xffffffa8
#define UBC_BASRB 0xffffffe8
#define UBC_BDRB 0xffffff90
#define UBC_BDMRB 0xffffff94
#define UBC_BRCR 0xffffff98
#endif
#endif /* __ASM_CPU_SH3_UBC_H */

64
arch/sh/include/cpu-sh4/cpu/ubc.h
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@ -1,64 +0,0 @@
/*
* include/asm-sh/cpu-sh4/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
* Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_UBC_H
#define __ASM_CPU_SH4_UBC_H
#if defined(CONFIG_CPU_SH4A)
#define UBC_CBR0 0xff200000
#define UBC_CRR0 0xff200004
#define UBC_CAR0 0xff200008
#define UBC_CAMR0 0xff20000c
#define UBC_CBR1 0xff200020
#define UBC_CRR1 0xff200024
#define UBC_CAR1 0xff200028
#define UBC_CAMR1 0xff20002c
#define UBC_CDR1 0xff200030
#define UBC_CDMR1 0xff200034
#define UBC_CETR1 0xff200038
#define UBC_CCMFR 0xff200600
#define UBC_CBCR 0xff200620
/* CBR */
#define UBC_CBR_AIE (0x01<<30)
#define UBC_CBR_ID_INST (0x01<<4)
#define UBC_CBR_RW_READ (0x01<<1)
#define UBC_CBR_CE (0x01)
#define UBC_CBR_AIV_MASK (0x00FF0000)
#define UBC_CBR_AIV_SHIFT (16)
#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
#define UBC_CBR_INIT 0x20000000
/* CRR */
#define UBC_CRR_RES (0x01<<13)
#define UBC_CRR_PCB (0x01<<1)
#define UBC_CRR_BIE (0x01)
#define UBC_CRR_INIT 0x00002000
#else /* CONFIG_CPU_SH4 */
#define UBC_BARA 0xff200000
#define UBC_BAMRA 0xff200004
#define UBC_BBRA 0xff200008
#define UBC_BASRA 0xff000014
#define UBC_BARB 0xff20000c
#define UBC_BAMRB 0xff200010
#define UBC_BBRB 0xff200014
#define UBC_BASRB 0xff000018
#define UBC_BDRB 0xff200018
#define UBC_BDMRB 0xff20001c
#define UBC_BRCR 0xff200020
#endif /* CONFIG_CPU_SH4 */
#endif /* __ASM_CPU_SH4_UBC_H */

20
arch/sh/kernel/cpu/init.c
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@ -24,9 +24,6 @@
#include <asm/elf.h>
#include <asm/io.h>
#include <asm/smp.h>
#ifdef CONFIG_SUPERH32
#include <asm/ubc.h>
#endif
/*
* Generic wrapper for command line arguments to disable on-chip
@ -252,20 +249,19 @@ static void __init dsp_init(void)
/**
* sh_cpu_init
*
* This is our initial entry point for each CPU, and is invoked on the boot
* CPU prior to calling start_kernel(). For SMP, a combination of this and
* start_secondary() will bring up each processor to a ready state prior
* to hand forking the idle loop.
* This is our initial entry point for each CPU, and is invoked on the
* boot CPU prior to calling start_kernel(). For SMP, a combination of
* this and start_secondary() will bring up each processor to a ready
* state prior to hand forking the idle loop.
*
* We do all of the basic processor init here, including setting up the
* caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
* hit (and subsequently platform_setup()) things like determining the
* CPU subtype and initial configuration will all be done.
* We do all of the basic processor init here, including setting up
* the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
* subsequently platform_setup()) things like determining the CPU
* subtype and initial configuration will all be done.
*
* Each processor family is still responsible for doing its own probing
* and cache configuration in detect_cpu_and_cache_system().
*/
asmlinkage void __init sh_cpu_init(void)
{
current_thread_info()->cpu = hard_smp_processor_id();

1
arch/sh/kernel/process_32.c
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@ -30,7 +30,6 @@
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
#include <asm/system.h>
#include <asm/ubc.h>
#include <asm/fpu.h>
#include <asm/syscalls.h>
#include <asm/watchdog.h>