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mmc: sdhci-pci-o2micro: Add SeaBird SeaEagle SD3 support
Add O2Micro/BayHubTech chip 8520 subversion B1 SD3.0 support. Add O2Micro/BayHubTech chip 8620 and 8621 SD3.0 support Enable Led function of 8520 chip. Signed-off-by: Peter Guo <peter.guo@bayhubtech.com> Signed-off-by: Adam Lee <adam.lee@canonical.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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@ -21,6 +21,45 @@
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#include "sdhci-pci.h"
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#include "sdhci-pci-o2micro.h"
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static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
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{
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u32 scratch_32;
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pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= value;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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}
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static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
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{
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int ret;
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u32 scratch_32;
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/* Set led of SD host function enable */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~O2_SD_FREG0_LEDOFF;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= O2_SD_LED_ENABLE;
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pci_write_config_dword(chip->pdev,
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O2_SD_TEST_REG, scratch_32);
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}
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void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
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{
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u32 scratch_32;
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@ -216,6 +255,40 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
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if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0,
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&scratch_32);
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scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
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/* Check Whether subId is 0x11 or 0x12 */
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if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
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scratch_32 = 0x2c280000;
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/* Set Base Clock to 208MZ */
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o2_pci_set_baseclk(chip, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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/* Enable Base Clk setting change */
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scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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scratch_32);
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/* Set Tuning Window to 4 */
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pci_write_config_byte(chip->pdev,
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O2_SD_TUNING_CTRL, 0x44);
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break;
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}
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}
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/* Enable 8520 led function */
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o2_pci_led_enable(chip);
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/* Set timeout CLK */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, &scratch_32);
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@ -276,7 +349,7 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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O2_SD_PLL_SETTING, &scratch_32);
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if ((scratch_32 & 0xff000000) == 0x01000000) {
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scratch_32 &= 0x0000FFFF;
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@ -299,6 +372,9 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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O2_SD_FUNC_REG4, scratch_32);
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}
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/* Set Tuning Windows to 5 */
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pci_write_config_byte(chip->pdev,
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O2_SD_TUNING_CTRL, 0x55);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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@ -57,6 +57,9 @@
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#define O2_SD_UHS2_L1_CTRL 0x35C
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#define O2_SD_FUNC_REG3 0x3E0
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#define O2_SD_FUNC_REG4 0x3E4
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#define O2_SD_LED_ENABLE BIT(6)
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#define O2_SD_FREG0_LEDOFF BIT(13)
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#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
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#define O2_SD_VENDOR_SETTING 0x110
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#define O2_SD_VENDOR_SETTING2 0x1C8
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