mirror of https://gitee.com/openkylin/linux.git
MIPS: AR7: Make ar7_register_devices much more durable
[Ralf: Fixed up the rejects and changed all the new printk(KERN_...); to pr_xxx() as suggested by Wu.] Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/920/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Alexander Clouter
Ralf Baechle
parent
632b629c0c
commit
7084338eb8
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@ -529,115 +529,130 @@ static struct platform_device ar7_wdt = {
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/*****************************************************************************
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* Init
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****************************************************************************/
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static int __init ar7_register_devices(void)
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static int __init ar7_register_uarts(void)
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{
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u16 chip_id;
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int res;
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u32 *bootcr, val;
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#ifdef CONFIG_SERIAL_8250
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static struct uart_port uart_port[2] __initdata;
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static struct uart_port uart_port __initdata;
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struct clk *bus_clk;
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int res;
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memset(uart_port, 0, sizeof(struct uart_port) * 2);
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memset(&uart_port, 0, sizeof(struct uart_port));
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bus_clk = clk_get(NULL, "bus");
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if (IS_ERR(bus_clk))
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panic("unable to get bus clk\n");
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uart_port[0].type = PORT_16550A;
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uart_port[0].line = 0;
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uart_port[0].irq = AR7_IRQ_UART0;
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uart_port[0].uartclk = clk_get_rate(bus_clk) / 2;
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uart_port[0].iotype = UPIO_MEM32;
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uart_port[0].mapbase = AR7_REGS_UART0;
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uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
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uart_port[0].regshift = 2;
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res = early_serial_setup(&uart_port[0]);
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uart_port.type = PORT_16550A;
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uart_port.uartclk = clk_get_rate(bus_clk) / 2;
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uart_port.iotype = UPIO_MEM32;
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uart_port.regshift = 2;
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uart_port.line = 0;
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uart_port.irq = AR7_IRQ_UART0;
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uart_port.mapbase = AR7_REGS_UART0;
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uart_port.membase = ioremap(uart_port.mapbase, 256);
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res = early_serial_setup(&uart_port);
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if (res)
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return res;
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/* Only TNETD73xx have a second serial port */
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if (ar7_has_second_uart()) {
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uart_port[1].type = PORT_16550A;
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uart_port[1].line = 1;
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uart_port[1].irq = AR7_IRQ_UART1;
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uart_port[1].uartclk = clk_get_rate(bus_clk) / 2;
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uart_port[1].iotype = UPIO_MEM32;
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uart_port[1].mapbase = UR8_REGS_UART1;
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uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
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uart_port[1].regshift = 2;
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res = early_serial_setup(&uart_port[1]);
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uart_port.line = 1;
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uart_port.irq = AR7_IRQ_UART1;
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uart_port.mapbase = UR8_REGS_UART1;
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uart_port.membase = ioremap(uart_port.mapbase, 256);
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res = early_serial_setup(&uart_port);
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if (res)
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return res;
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}
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#endif /* CONFIG_SERIAL_8250 */
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#endif
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return 0;
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}
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static int __init ar7_register_devices(void)
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{
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void __iomem *bootcr;
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u32 val;
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u16 chip_id;
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int res;
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res = ar7_register_uarts();
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if (res)
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pr_err("unable to setup uart(s): %d\n", res);
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res = platform_device_register(&physmap_flash);
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if (res)
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return res;
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pr_warning("unable to register physmap-flash: %d\n", res);
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ar7_device_disable(vlynq_low_data.reset_bit);
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res = platform_device_register(&vlynq_low);
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if (res)
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return res;
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pr_warning("unable to register vlynq-low: %d\n", res);
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if (ar7_has_high_vlynq()) {
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ar7_device_disable(vlynq_high_data.reset_bit);
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res = platform_device_register(&vlynq_high);
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if (res)
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return res;
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pr_warning("unable to register vlynq-high: %d\n", res);
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}
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if (ar7_has_high_cpmac()) {
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res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status);
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if (res && res != -ENODEV)
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return res;
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cpmac_get_mac(1, cpmac_high_data.dev_addr);
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res = platform_device_register(&cpmac_high);
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if (res)
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return res;
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} else {
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if (!res) {
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cpmac_get_mac(1, cpmac_high_data.dev_addr);
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res = platform_device_register(&cpmac_high);
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if (res)
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pr_warning("unable to register cpmac-high: %d\n", res);
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} else
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pr_warning("unable to add cpmac-high phy: %d\n", res);
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} else
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cpmac_low_data.phy_mask = 0xffffffff;
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}
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res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
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if (res && res != -ENODEV)
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return res;
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cpmac_get_mac(0, cpmac_low_data.dev_addr);
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res = platform_device_register(&cpmac_low);
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if (res)
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return res;
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if (!res) {
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cpmac_get_mac(0, cpmac_low_data.dev_addr);
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res = platform_device_register(&cpmac_low);
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if (res)
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pr_warning("unable to register cpmac-low: %d\n", res);
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} else
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pr_warning("unable to add cpmac-low phy: %d\n", res);
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detect_leds();
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res = platform_device_register(&ar7_gpio_leds);
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if (res)
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return res;
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pr_warning("unable to register leds: %d\n", res);
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res = platform_device_register(&ar7_udc);
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chip_id = ar7_chip_id();
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switch (chip_id) {
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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ar7_wdt_res.start = AR7_REGS_WDT;
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break;
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case AR7_CHIP_7300:
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ar7_wdt_res.start = UR8_REGS_WDT;
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break;
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default:
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break;
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}
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ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
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bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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val = *bootcr;
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iounmap(bootcr);
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if (res)
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pr_warning("unable to register usb slave: %d\n", res);
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/* Register watchdog only if enabled in hardware */
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if (val & AR7_WDT_HW_ENA)
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res = platform_device_register(&ar7_wdt);
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bootcr = ioremap_nocache(AR7_REGS_DCL, 4);
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val = readl(bootcr);
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iounmap(bootcr);
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if (val & AR7_WDT_HW_ENA) {
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chip_id = ar7_chip_id();
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switch (chip_id) {
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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ar7_wdt_res.start = AR7_REGS_WDT;
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break;
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case AR7_CHIP_7300:
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ar7_wdt_res.start = UR8_REGS_WDT;
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break;
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default:
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break;
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}
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return res;
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ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
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res = platform_device_register(&ar7_wdt);
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if (res)
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pr_warning("unable to register watchdog: %d\n", res);
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}
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return 0;
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}
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arch_initcall(ar7_register_devices);
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