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drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit 

SKL and BXT have the same snippets of code for enabling disabling the
DBUF. Extract those into helpers and move the calls from
init/unit_cdclk() to the display core init/init since this stuff isn't
really about cdclk. Also doing the enable twice shouldn't hurt since
you're just setting the request bit again when it was already set.

We can also toss in a few WARNs about the register values into
skl_get_dpll0_vco() now that we know that things should always be
sane there.

Flatten skl_init_cdclk() while at it.

v2: s/skl/gen9/ in function names (Imre)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-12-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä 2016-05-13 23:41:30 +03:00
parent 9f7eb31af2
commit 70c2c18406
2 changed files with 38 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
drivers/gpu/drm/i915/intel_display.c
View File

@ -5400,18 +5400,6 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
/* TODO: Check for a valid CDCLK rate */
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
return false;
}
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
return false;
}
return true;
}
@ -5438,26 +5426,10 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
* here, it belongs to modeset time
*/
broxton_set_cdclk(dev_priv, 624000);
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
udelay(10);
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout!\n");
}
void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
udelay(10);
if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
DRM_ERROR("DBuf power disable timeout!\n");
/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
broxton_set_cdclk(dev_priv, 19200);
}
@ -5679,15 +5651,6 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
{
/* disable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
udelay(10);
if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
DRM_ERROR("DBuf power disable timeout\n");
skl_set_cdclk(dev_priv, 24000, 0);
}
@ -5705,24 +5668,15 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
if (dev_priv->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
dev_priv->skl_vco_freq);
} else {
/* set CDCLK to the lowest frequency, Modeset follows */
vco = dev_priv->skl_preferred_vco_freq;
if (vco == 0)
vco = 8100;
cdclk = skl_calc_cdclk(0, vco);
skl_set_cdclk(dev_priv, cdclk, vco);
return;
}
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
vco = dev_priv->skl_preferred_vco_freq;
if (vco == 0)
vco = 8100;
cdclk = skl_calc_cdclk(0, vco);
udelay(10);
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout\n");
skl_set_cdclk(dev_priv, cdclk, vco);
}
static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)

32
drivers/gpu/drm/i915/intel_runtime_pm.c
View File

@ -2176,6 +2176,28 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_unlock(&power_domains->lock);
}
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
udelay(10);
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout\n");
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL);
udelay(10);
if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
DRM_ERROR("DBuf power disable timeout!\n");
}
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
@ -2202,6 +2224,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
if (resume && dev_priv->csr.dmc_payload)
intel_csr_load_program(dev_priv);
}
@ -2213,6 +2237,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
gen9_dbuf_disable(dev_priv);
skl_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
@ -2257,6 +2283,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
broxton_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
broxton_ddi_phy_init(dev_priv);
broxton_cdclk_verify_state(dev_priv);
@ -2274,6 +2303,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
broxton_ddi_phy_uninit(dev_priv);
gen9_dbuf_disable(dev_priv);
broxton_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */