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ARM: IMX31: configure pins iomux for SDHC setup on litekit board. 

This patch adds SDHC support, and corrects current pins setup.
Added irq handling on card removal.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
Cc: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Vladimir Zapolskiy 2010-01-26 14:00:40 +03:00 committed by Sascha Hauer
parent 4e41db871e
commit 70c91a3849
1 changed files with 21 additions and 9 deletions
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30
arch/arm/mach-mx3/mx31lite-db.c
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@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = {
MX31_PIN_CSPI1_SS0__SS0, MX31_PIN_CSPI1_SS0__SS0,
MX31_PIN_CSPI1_SS1__SS1, MX31_PIN_CSPI1_SS1__SS1,
MX31_PIN_CSPI1_SS2__SS2, MX31_PIN_CSPI1_SS2__SS2,
/* SDHC1 */
MX31_PIN_SD1_DATA0__SD1_DATA0,
MX31_PIN_SD1_DATA1__SD1_DATA1,
MX31_PIN_SD1_DATA2__SD1_DATA2,
MX31_PIN_SD1_DATA3__SD1_DATA3,
MX31_PIN_SD1_CLK__SD1_CLK,
MX31_PIN_SD1_CMD__SD1_CMD,
}; };
/* UART */ /* UART */
@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = {
static int gpio_det, gpio_wp; static int gpio_det, gpio_wp;
#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) PAD_CTL_ODE_CMOS)
static int mxc_mmc1_get_ro(struct device *dev) static int mxc_mmc1_get_ro(struct device *dev)
{ {
return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
} }
static int mxc_mmc1_init(struct device *dev, static int mxc_mmc1_init(struct device *dev,
@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev,
gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
ret = gpio_request(gpio_det, "MMC detect"); ret = gpio_request(gpio_det, "MMC detect");
if (ret) if (ret)
@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_wp); gpio_direction_input(gpio_wp);
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC detect", data); "MMC detect", data);
if (ret) if (ret)
goto exit_free_wp; goto exit_free_wp;
@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{ {
gpio_free(gpio_det); gpio_free(gpio_det);
gpio_free(gpio_wp); gpio_free(gpio_wp);
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
} }
static struct imxmmc_platform_data mmc_pdata = { static struct imxmmc_platform_data mmc_pdata = {