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stmmac: pci: split out common_default_data() helper 

New helper is added in order to prevent misconfiguration happened
for one of the platforms when configuration data is expanded.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Andy Shevchenko 2017-05-08 17:14:22 +03:00 committed by David S. Miller
parent efcd24147f
commit 70fe4432bb
1 changed files with 18 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
View File

@ -70,11 +70,8 @@ static int stmmac_pci_find_phy_addr(struct stmmac_pci_info *info)
return -ENODEV; return -ENODEV;
} }
static void stmmac_default_data(struct plat_stmmacenet_data *plat) static void common_default_data(struct plat_stmmacenet_data *plat)
{ {
plat->bus_id = 1;
plat->phy_addr = 0;
plat->interface = PHY_INTERFACE_MODE_GMII;
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->has_gmac = 1; plat->has_gmac = 1;
plat->force_sf_dma_mode = 1; plat->force_sf_dma_mode = 1;
@ -82,10 +79,6 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat)
plat->mdio_bus_data->phy_reset = NULL; plat->mdio_bus_data->phy_reset = NULL;
plat->mdio_bus_data->phy_mask = 0; plat->mdio_bus_data->phy_mask = 0;
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
/* TODO: AXI */
/* Set default value for multicast hash bins */ /* Set default value for multicast hash bins */
plat->multicast_filter_bins = HASH_TABLE_SIZE; plat->multicast_filter_bins = HASH_TABLE_SIZE;
@ -107,12 +100,29 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat)
plat->rx_queues_cfg[0].pkt_route = 0x0; plat->rx_queues_cfg[0].pkt_route = 0x0;
} }
static void stmmac_default_data(struct plat_stmmacenet_data *plat)
{
/* Set common default data first */
common_default_data(plat);
plat->bus_id = 1;
plat->phy_addr = 0;
plat->interface = PHY_INTERFACE_MODE_GMII;
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
/* TODO: AXI */
}
static int quark_default_data(struct plat_stmmacenet_data *plat, static int quark_default_data(struct plat_stmmacenet_data *plat,
struct stmmac_pci_info *info) struct stmmac_pci_info *info)
{ {
struct pci_dev *pdev = info->pdev; struct pci_dev *pdev = info->pdev;
int ret; int ret;
/* Set common default data first */
common_default_data(plat);
/* /*
* Refuse to load the driver and register net device if MAC controller * Refuse to load the driver and register net device if MAC controller
* does not connect to any PHY interface. * does not connect to any PHY interface.
@ -124,38 +134,12 @@ static int quark_default_data(struct plat_stmmacenet_data *plat,
plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn); plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn);
plat->phy_addr = ret; plat->phy_addr = ret;
plat->interface = PHY_INTERFACE_MODE_RMII; plat->interface = PHY_INTERFACE_MODE_RMII;
plat->clk_csr = 2;
plat->has_gmac = 1;
plat->force_sf_dma_mode = 1;
plat->mdio_bus_data->phy_reset = NULL;
plat->mdio_bus_data->phy_mask = 0;
plat->dma_cfg->pbl = 16; plat->dma_cfg->pbl = 16;
plat->dma_cfg->pblx8 = true; plat->dma_cfg->pblx8 = true;
plat->dma_cfg->fixed_burst = 1; plat->dma_cfg->fixed_burst = 1;
/* AXI (TODO) */ /* AXI (TODO) */
/* Set default value for multicast hash bins */
plat->multicast_filter_bins = HASH_TABLE_SIZE;
/* Set default value for unicast filter entries */
plat->unicast_filter_entries = 1;
/* Set the maxmtu to a default of JUMBO_LEN */
plat->maxmtu = JUMBO_LEN;
/* Set default number of RX and TX queues to use */
plat->tx_queues_to_use = 1;
plat->rx_queues_to_use = 1;
/* Disable Priority config by default */
plat->tx_queues_cfg[0].use_prio = false;
plat->rx_queues_cfg[0].use_prio = false;
/* Disable RX queues routing by default */
plat->rx_queues_cfg[0].pkt_route = 0x0;
return 0; return 0;
} }