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drm/nouveau: Fix indentation-related checkpatch.pl error messages. 

Fix 'ERROR: code indent should use tabs where possible'
Fix 'ERROR: space required before the open parenthesis ('

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Emil Velikov 2011-03-19 23:31:51 +00:00 committed by Ben Skeggs
parent 01e542c65d
commit 71298e2f0b
4 changed files with 21 additions and 21 deletions
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4
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -887,13 +887,13 @@ extern void nouveau_channel_idle(struct nouveau_channel *chan);
int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
if (ret) \ if (ret) \
return ret; \ return ret; \
} while(0) } while (0)
#define NVOBJ_MTHD(d,c,m,e) do { \ #define NVOBJ_MTHD(d,c,m,e) do { \
int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
if (ret) \ if (ret) \
return ret; \ return ret; \
} while(0) } while (0)
extern int nouveau_gpuobj_early_init(struct drm_device *); extern int nouveau_gpuobj_early_init(struct drm_device *);
extern int nouveau_gpuobj_init(struct drm_device *); extern int nouveau_gpuobj_init(struct drm_device *);

14
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -599,7 +599,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
/* Get "some number" from the timing reg for NV_40 /* Get "some number" from the timing reg for NV_40
* Used in calculations later */ * Used in calculations later */
if(dev_priv->card_type == NV_40) { if (dev_priv->card_type == NV_40) {
magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24; magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
} }
@ -645,22 +645,22 @@ nouveau_mem_timing_init(struct drm_device *dev)
timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 | timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
tUNK_18 << 16 | tUNK_18 << 16 |
(tUNK_1 + tUNK_19 + 1 + magic_number) << 8; (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
if(dev_priv->chipset == 0xa8) { if (dev_priv->chipset == 0xa8) {
timing->reg_100224 |= (tUNK_2 - 1); timing->reg_100224 |= (tUNK_2 - 1);
} else { } else {
timing->reg_100224 |= (tUNK_2 + 2 - magic_number); timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
} }
timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) { if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
timing->reg_100228 |= (tUNK_19 - 1) << 24; timing->reg_100228 |= (tUNK_19 - 1) << 24;
} }
if(dev_priv->card_type == NV_40) { if (dev_priv->card_type == NV_40) {
/* NV40: don't know what the rest of the regs are.. /* NV40: don't know what the rest of the regs are..
* And don't need to know either */ * And don't need to know either */
timing->reg_100228 |= 0x20200000 | magic_number << 24; timing->reg_100228 |= 0x20200000 | magic_number << 24;
} else if(dev_priv->card_type >= NV_50) { } else if (dev_priv->card_type >= NV_50) {
/* XXX: reg_10022c */ /* XXX: reg_10022c */
timing->reg_10022c = tUNK_2 - 1; timing->reg_10022c = tUNK_2 - 1;
@ -670,7 +670,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
timing->reg_100234 = (tRAS << 24 | tRC); timing->reg_100234 = (tRAS << 24 | tRC);
timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
if(dev_priv->chipset < 0xa3) { if (dev_priv->chipset < 0xa3) {
timing->reg_100234 |= (tUNK_2 + 2) << 8; timing->reg_100234 |= (tUNK_2 + 2) << 8;
} else { } else {
/* XXX: +6? */ /* XXX: +6? */
@ -681,7 +681,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
* reg_100238: 0x00?????? * reg_100238: 0x00??????
* reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */ * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
timing->reg_10023c = 0x202; timing->reg_10023c = 0x202;
if(dev_priv->chipset < 0xa3) { if (dev_priv->chipset < 0xa3) {
timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16; timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
} else { } else {
/* currently unknown /* currently unknown

4
drivers/gpu/drm/nouveau/nv50_grctx.c
View File

@ -747,7 +747,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
gr_def(ctx, offset + 0x64, 0x0000001f); gr_def(ctx, offset + 0x64, 0x0000001f);
gr_def(ctx, offset + 0x68, 0x0000000f); gr_def(ctx, offset + 0x68, 0x0000000f);
gr_def(ctx, offset + 0x6c, 0x0000000f); gr_def(ctx, offset + 0x6c, 0x0000000f);
} else if(dev_priv->chipset < 0xa0) { } else if (dev_priv->chipset < 0xa0) {
cp_ctx(ctx, offset + 0x50, 1); cp_ctx(ctx, offset + 0x50, 1);
cp_ctx(ctx, offset + 0x70, 1); cp_ctx(ctx, offset + 0x70, 1);
} else { } else {
@ -2836,7 +2836,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
if (IS_NVA3F(dev_priv->chipset)) if (IS_NVA3F(dev_priv->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
if(dev_priv->chipset == 0x50) if (dev_priv->chipset == 0x50)
xf_emit(ctx, 1, 0); /* ff */ xf_emit(ctx, 1, 0); /* ff */
else else
xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ xf_emit(ctx, 3, 0); /* 1, 7, 3ff */