mirror of https://gitee.com/openkylin/linux.git
iwlwifi: unite macros with same meaning
TFD_*_SLOTS and IWL_*_QUEUE_SIZE both define the TX queue size (number of TFDs). Get rid of TFD_*_SLOTS and use only IWL_*_QUEUE_SIZE. Signed-off-by: Shaul Triebitz <shaul.triebitz@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -8,6 +8,7 @@
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* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -30,6 +31,7 @@
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -133,6 +135,7 @@ enum iwl_tx_queue_cfg_actions {
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#define IWL_DEFAULT_QUEUE_SIZE 256
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#define IWL_MGMT_QUEUE_SIZE 16
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#define IWL_CMD_QUEUE_SIZE 32
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/**
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* struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command
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* @sta_id: station id
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@ -66,7 +66,8 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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void *iml_img;
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u32 control_flags = 0;
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int ret;
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int cmdq_size = max_t(u32, TFD_CMD_SLOTS, trans->cfg->min_txq_size);
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int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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/* Allocate prph scratch */
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prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -210,7 +210,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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ctxt_info->hcmd_cfg.cmd_queue_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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ctxt_info->hcmd_cfg.cmd_queue_size =
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TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);
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TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
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@ -290,10 +290,6 @@ struct iwl_cmd_meta {
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u32 tbs;
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};
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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/*
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* The FH will write back to the first TB only, so we need to copy some data
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* into the buffer regardless of whether it should be mapped or not.
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -234,7 +234,8 @@ void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
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static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int queue_size = max_t(u32, TFD_CMD_SLOTS, trans->cfg->min_txq_size);
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int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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/* TODO: most of the logic can be removed in A0 - but not in Z0 */
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spin_lock(&trans_pcie->irq_lock);
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@ -996,10 +996,10 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
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bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
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if (cmd_queue)
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slots_num = max_t(u32, TFD_CMD_SLOTS,
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slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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else
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slots_num = max_t(u32, TFD_TX_CMD_SLOTS,
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slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
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trans->cfg->min_256_ba_txq_size);
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trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
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ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
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@ -1050,10 +1050,10 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
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bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
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if (cmd_queue)
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slots_num = max_t(u32, TFD_CMD_SLOTS,
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slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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else
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slots_num = max_t(u32, TFD_TX_CMD_SLOTS,
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slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
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trans->cfg->min_256_ba_txq_size);
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ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
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slots_num, cmd_queue);
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