mirror of https://gitee.com/openkylin/linux.git
MIPS: Fixup ordering of micro assembler instructions.
A number of new instructions have been added to the micro assembler causing the list to no longer be in alphabetical order. This patch fixes up the name ordering. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Steven J. Hill
Ralf Baechle
parent
bb0757ebb9
commit
71a1c776d5
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@ -6,6 +6,7 @@
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc.
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*/
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#include <linux/types.h>
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@ -62,8 +63,10 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
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Ip_u2u1s3(_addiu);
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Ip_u3u1u2(_addu);
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Ip_u2u1u3(_andi);
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Ip_u3u1u2(_and);
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Ip_u2u1u3(_andi);
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Ip_u1u2s3(_bbit0);
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Ip_u1u2s3(_bbit1);
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Ip_u1u2s3(_beq);
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Ip_u1u2s3(_beql);
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Ip_u1s2(_bgez);
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@ -72,55 +75,54 @@ Ip_u1s2(_bltz);
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Ip_u1s2(_bltzl);
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Ip_u1u2s3(_bne);
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Ip_u2s3u1(_cache);
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Ip_u1u2u3(_dmfc0);
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Ip_u1u2u3(_dmtc0);
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Ip_u2u1s3(_daddiu);
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Ip_u3u1u2(_daddu);
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Ip_u2u1msbu3(_dins);
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Ip_u2u1msbu3(_dinsm);
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Ip_u1u2u3(_dmfc0);
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Ip_u1u2u3(_dmtc0);
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Ip_u2u1u3(_drotr);
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Ip_u2u1u3(_drotr32);
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Ip_u2u1u3(_dsll);
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Ip_u2u1u3(_dsll32);
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Ip_u2u1u3(_dsra);
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Ip_u2u1u3(_dsrl);
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Ip_u2u1u3(_dsrl32);
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Ip_u2u1u3(_drotr);
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Ip_u2u1u3(_drotr32);
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Ip_u3u1u2(_dsubu);
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Ip_0(_eret);
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Ip_u1(_j);
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Ip_u1(_jal);
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Ip_u1(_jr);
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Ip_u2s3u1(_ld);
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Ip_u3u1u2(_ldx);
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Ip_u2s3u1(_ll);
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Ip_u2s3u1(_lld);
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Ip_u1s2(_lui);
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Ip_u2s3u1(_lw);
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Ip_u3u1u2(_lwx);
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Ip_u1u2u3(_mfc0);
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Ip_u1u2u3(_mtc0);
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Ip_u2u1u3(_ori);
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Ip_u3u1u2(_or);
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Ip_u2u1u3(_ori);
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Ip_u2s3u1(_pref);
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Ip_0(_rfe);
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Ip_u2u1u3(_rotr);
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Ip_u2s3u1(_sc);
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Ip_u2s3u1(_scd);
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Ip_u2s3u1(_sd);
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Ip_u2u1u3(_sll);
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Ip_u2u1u3(_sra);
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Ip_u2u1u3(_srl);
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Ip_u2u1u3(_rotr);
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Ip_u3u1u2(_subu);
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Ip_u2s3u1(_sw);
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Ip_u1(_syscall);
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Ip_0(_tlbp);
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Ip_0(_tlbr);
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Ip_0(_tlbwi);
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Ip_0(_tlbwr);
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Ip_u3u1u2(_xor);
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Ip_u2u1u3(_xori);
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Ip_u2u1msbu3(_dins);
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Ip_u2u1msbu3(_dinsm);
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Ip_u1(_syscall);
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Ip_u1u2s3(_bbit0);
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Ip_u1u2s3(_bbit1);
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Ip_u3u1u2(_lwx);
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Ip_u3u1u2(_ldx);
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/* Handle labels. */
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struct uasm_label {
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@ -145,37 +147,37 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
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/* convenience macros for instructions */
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#ifdef CONFIG_64BIT
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# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
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# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
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# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
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# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
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# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
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# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
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# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
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# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
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# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
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# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
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# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
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# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
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# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
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# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
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# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
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# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
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# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
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# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
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# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
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# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
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# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
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# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
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# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
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# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
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#else
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# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
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# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
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# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
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# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
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# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
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# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
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# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
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# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
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# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
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# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
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# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
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# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
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# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
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# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
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# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
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# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
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# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
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# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
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# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
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# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
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# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
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# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
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# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
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# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
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#endif
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#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
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@ -183,19 +185,10 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
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#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
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#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
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#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
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#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
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#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
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#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
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#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
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#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
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static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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{
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if (a3 < 32)
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uasm_i_dsrl(p, a1, a2, a3);
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else
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uasm_i_dsrl32(p, a1, a2, a3 - 32);
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}
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static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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@ -215,6 +208,15 @@ static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
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uasm_i_dsll32(p, a1, a2, a3 - 32);
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}
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static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
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unsigned int a2, unsigned int a3)
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{
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if (a3 < 32)
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uasm_i_dsrl(p, a1, a2, a3);
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else
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uasm_i_dsrl32(p, a1, a2, a3 - 32);
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}
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/* Handle relocations. */
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struct uasm_reloc {
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u32 *addr;
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@ -234,16 +236,16 @@ void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
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int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
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/* Convenience functions for labeled branches. */
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void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
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void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
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unsigned int reg2, int lid);
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void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
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unsigned int bit, int lid);
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void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
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unsigned int bit, int lid);
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void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
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unsigned int reg2, int lid);
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void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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@ -58,18 +58,16 @@ enum fields {
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enum opcode {
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insn_invalid,
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insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
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insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
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insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
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insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
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insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
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insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
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insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
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insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
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insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
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insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
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insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
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insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
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insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
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insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
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insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld,
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insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori,
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insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
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insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp,
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insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
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insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,
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insn_lwx, insn_ldx
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};
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struct insn {
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@ -90,65 +88,65 @@ struct insn {
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static struct insn insn_table[] __uasminitdata = {
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{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
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{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
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{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
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{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
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{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
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{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
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{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
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{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
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{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
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{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
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{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
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{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
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{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
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{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
|
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{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
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{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
|
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
|
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{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
|
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
|
||||
{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
|
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{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
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{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
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{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
|
||||
{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
|
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
|
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{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
|
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{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
|
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{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
|
||||
{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
|
||||
{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
|
||||
{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
|
||||
{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
|
||||
{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
|
||||
{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
|
||||
{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
|
||||
{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
|
||||
{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
|
||||
{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
|
||||
{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
|
||||
{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
|
||||
{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
|
||||
{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
|
||||
{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
|
||||
{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
|
||||
{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
|
||||
{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
|
||||
{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
|
||||
{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
|
||||
{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
|
||||
{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
|
||||
{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
|
||||
{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
|
||||
{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
|
||||
{ insn_invalid, 0, 0 }
|
||||
};
|
||||
|
||||
|
|
|
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Loading…
Reference in New Issue