mirror of https://gitee.com/openkylin/linux.git
edac: altera: Add Altera SDRAM EDAC support
This patch adds support for the CycloneV and ArriaV SDRAM controllers. Correction and reporting of SBEs, Panic on DBEs. There was a discussion thread on whether this driver should be an mfd driver or just make use of syscon, which is already a mfd. Ultimately, the decision to use a simple syscon interface was reached.[1] [1] https://lkml.org/lkml/2014/7/30/514 [dinguyen] Fixed Kconfig to have EDAC_ALTERA_MC as a tristate to prevent a build failure for allmodconfig. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Borislav Petkov <bp@suse.de> [dinguyen] cleaned up commit message Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Thor Thayer
Dinh Nguyen
parent
52addcf9d6
commit
71bcada88b
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@ -1376,6 +1376,11 @@ M: Dinh Nguyen <dinguyen@altera.com>
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S: Maintained
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F: drivers/clk/socfpga/
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ARM/SOCFPGA EDAC SUPPORT
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M: Thor Thayer <tthayer@opensource.altera.com>
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S: Maintained
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F: drivers/edac/altera_edac.
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ARM/STI ARCHITECTURE
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M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
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M: Maxime Coquelin <maxime.coquelin@st.com>
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@ -376,4 +376,13 @@ config EDAC_OCTEON_PCI
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_ALTERA_MC
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tristate "Altera SDRAM Memory Controller EDAC"
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depends on EDAC_MM_EDAC && ARCH_SOCFPGA
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help
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Support for error detection and correction on the
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Altera SDRAM memory controller. Note that the
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preloader must initialize the SDRAM before loading
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the kernel.
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endif # EDAC
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@ -65,3 +65,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC) += octeon_edac-pc.o
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obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
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obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o
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obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o
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obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o
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@ -0,0 +1,410 @@
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/*
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* Copyright Altera Corporation (C) 2014. All rights reserved.
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Adapted from the highbank_mc_edac driver.
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*/
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#include <linux/ctype.h>
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#include <linux/edac.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#define EDAC_MOD_STR "altera_edac"
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#define EDAC_VERSION "1"
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/* SDRAM Controller CtrlCfg Register */
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#define CTLCFG_OFST 0x00
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/* SDRAM Controller CtrlCfg Register Bit Masks */
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#define CTLCFG_ECC_EN 0x400
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#define CTLCFG_ECC_CORR_EN 0x800
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#define CTLCFG_GEN_SB_ERR 0x2000
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#define CTLCFG_GEN_DB_ERR 0x4000
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#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
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CTLCFG_ECC_CORR_EN)
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/* SDRAM Controller Address Width Register */
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#define DRAMADDRW_OFST 0x2C
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/* SDRAM Controller Address Widths Field Register */
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#define DRAMADDRW_COLBIT_MASK 0x001F
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#define DRAMADDRW_COLBIT_SHIFT 0
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#define DRAMADDRW_ROWBIT_MASK 0x03E0
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#define DRAMADDRW_ROWBIT_SHIFT 5
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#define DRAMADDRW_BANKBIT_MASK 0x1C00
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#define DRAMADDRW_BANKBIT_SHIFT 10
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#define DRAMADDRW_CSBIT_MASK 0xE000
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#define DRAMADDRW_CSBIT_SHIFT 13
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/* SDRAM Controller Interface Data Width Register */
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#define DRAMIFWIDTH_OFST 0x30
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/* SDRAM Controller Interface Data Width Defines */
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#define DRAMIFWIDTH_16B_ECC 24
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#define DRAMIFWIDTH_32B_ECC 40
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/* SDRAM Controller DRAM Status Register */
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#define DRAMSTS_OFST 0x38
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/* SDRAM Controller DRAM Status Register Bit Masks */
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#define DRAMSTS_SBEERR 0x04
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#define DRAMSTS_DBEERR 0x08
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#define DRAMSTS_CORR_DROP 0x10
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/* SDRAM Controller DRAM IRQ Register */
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#define DRAMINTR_OFST 0x3C
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/* SDRAM Controller DRAM IRQ Register Bit Masks */
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#define DRAMINTR_INTREN 0x01
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#define DRAMINTR_SBEMASK 0x02
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#define DRAMINTR_DBEMASK 0x04
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#define DRAMINTR_CORRDROPMASK 0x08
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#define DRAMINTR_INTRCLR 0x10
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/* SDRAM Controller Single Bit Error Count Register */
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#define SBECOUNT_OFST 0x40
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/* SDRAM Controller Single Bit Error Count Register Bit Masks */
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#define SBECOUNT_MASK 0x0F
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/* SDRAM Controller Double Bit Error Count Register */
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#define DBECOUNT_OFST 0x44
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/* SDRAM Controller Double Bit Error Count Register Bit Masks */
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#define DBECOUNT_MASK 0x0F
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/* SDRAM Controller ECC Error Address Register */
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#define ERRADDR_OFST 0x48
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/* SDRAM Controller ECC Error Address Register Bit Masks */
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#define ERRADDR_MASK 0xFFFFFFFF
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/* Altera SDRAM Memory Controller data */
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struct altr_sdram_mc_data {
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struct regmap *mc_vbase;
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};
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static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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u32 status, err_count, err_addr;
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/* Error Address is shared by both SBE & DBE */
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regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr);
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regmap_read(drvdata->mc_vbase, DRAMSTS_OFST, &status);
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if (status & DRAMSTS_DBEERR) {
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regmap_read(drvdata->mc_vbase, DBECOUNT_OFST, &err_count);
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panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
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err_count, err_addr);
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}
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if (status & DRAMSTS_SBEERR) {
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regmap_read(drvdata->mc_vbase, SBECOUNT_OFST, &err_count);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
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err_addr >> PAGE_SHIFT,
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err_addr & ~PAGE_MASK, 0,
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0, 0, -1, mci->ctl_name, "");
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}
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regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
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(DRAMINTR_INTRCLR | DRAMINTR_INTREN));
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_EDAC_DEBUG
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static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
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const char __user *data,
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size_t count, loff_t *ppos)
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{
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struct mem_ctl_info *mci = file->private_data;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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u32 *ptemp;
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dma_addr_t dma_handle;
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u32 reg, read_reg;
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ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
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if (!ptemp) {
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dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
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edac_printk(KERN_ERR, EDAC_MC,
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"Inject: Buffer Allocation error\n");
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return -ENOMEM;
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}
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regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg);
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read_reg &= ~(CTLCFG_GEN_SB_ERR | CTLCFG_GEN_DB_ERR);
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/* Error are injected by writing a word while the SBE or DBE
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* bit in the CTLCFG register is set. Reading the word will
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* trigger the SBE or DBE error and the corresponding IRQ.
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*/
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if (count == 3) {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Double bit error\n");
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
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(read_reg | CTLCFG_GEN_DB_ERR));
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} else {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Single bit error\n");
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
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(read_reg | CTLCFG_GEN_SB_ERR));
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}
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ptemp[0] = 0x5A5A5A5A;
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ptemp[1] = 0xA5A5A5A5;
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/* Clear the error injection bits */
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST, read_reg);
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/* Ensure it has been written out */
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wmb();
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/*
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* To trigger the error, we need to read the data back
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* (the data was written with errors above).
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* The ACCESS_ONCE macros and printk are used to prevent the
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* the compiler optimizing these reads out.
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*/
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reg = ACCESS_ONCE(ptemp[0]);
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read_reg = ACCESS_ONCE(ptemp[1]);
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/* Force Read */
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rmb();
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edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
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reg, read_reg);
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dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
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return count;
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}
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static const struct file_operations altr_sdr_mc_debug_inject_fops = {
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.open = simple_open,
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.write = altr_sdr_mc_err_inject_write,
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.llseek = generic_file_llseek,
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};
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static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
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{
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if (mci->debugfs)
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debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
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&altr_sdr_mc_debug_inject_fops);
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}
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#else
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static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
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{}
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#endif
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/* Get total memory size in bytes */
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static u32 altr_sdram_get_total_mem_size(struct regmap *mc_vbase)
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{
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u32 size, read_reg, row, bank, col, cs, width;
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if (regmap_read(mc_vbase, DRAMADDRW_OFST, &read_reg) < 0)
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return 0;
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if (regmap_read(mc_vbase, DRAMIFWIDTH_OFST, &width) < 0)
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return 0;
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col = (read_reg & DRAMADDRW_COLBIT_MASK) >>
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DRAMADDRW_COLBIT_SHIFT;
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row = (read_reg & DRAMADDRW_ROWBIT_MASK) >>
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DRAMADDRW_ROWBIT_SHIFT;
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bank = (read_reg & DRAMADDRW_BANKBIT_MASK) >>
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DRAMADDRW_BANKBIT_SHIFT;
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cs = (read_reg & DRAMADDRW_CSBIT_MASK) >>
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DRAMADDRW_CSBIT_SHIFT;
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/* Correct for ECC as its not addressible */
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if (width == DRAMIFWIDTH_32B_ECC)
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width = 32;
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if (width == DRAMIFWIDTH_16B_ECC)
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width = 16;
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/* calculate the SDRAM size base on this info */
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size = 1 << (row + bank + col);
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size = size * cs * (width / 8);
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return size;
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}
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static int altr_sdram_probe(struct platform_device *pdev)
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{
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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struct altr_sdram_mc_data *drvdata;
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struct regmap *mc_vbase;
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struct dimm_info *dimm;
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u32 read_reg, mem_size;
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int irq;
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int res = 0;
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/* Validate the SDRAM controller has ECC enabled */
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/* Grab the register range from the sdr controller in device tree */
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mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"altr,sdr-syscon");
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if (IS_ERR(mc_vbase)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"regmap for altr,sdr-syscon lookup failed.\n");
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return -ENODEV;
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}
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if (regmap_read(mc_vbase, CTLCFG_OFST, &read_reg) ||
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((read_reg & CTLCFG_ECC_AUTO_EN) != CTLCFG_ECC_AUTO_EN)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No ECC/ECC disabled [0x%08X]\n", read_reg);
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return -ENODEV;
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}
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/* Grab memory size from device tree. */
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mem_size = altr_sdram_get_total_mem_size(mc_vbase);
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if (!mem_size) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to calculate memory size\n");
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return -ENODEV;
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}
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/* Ensure the SDRAM Interrupt is disabled and cleared */
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if (regmap_write(mc_vbase, DRAMINTR_OFST, DRAMINTR_INTRCLR)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC IRQ\n");
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return -ENODEV;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No irq %d in DT\n", irq);
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return -ENODEV;
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}
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 1;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = 1;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct altr_sdram_mc_data));
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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drvdata = mci->pvt_info;
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drvdata->mc_vbase = mc_vbase;
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platform_set_drvdata(pdev, mci);
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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res = -ENOMEM;
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goto free;
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}
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = EDAC_VERSION;
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mci->ctl_name = dev_name(&pdev->dev);
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mci->scrub_mode = SCRUB_SW_SRC;
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mci->dev_name = dev_name(&pdev->dev);
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dimm = *mci->dimms;
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dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
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dimm->grain = 8;
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dimm->dtype = DEV_X8;
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dimm->mtype = MEM_DDR3;
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dimm->edac_mode = EDAC_SECDED;
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res = edac_mc_add_mc(mci);
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if (res < 0)
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goto err;
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res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
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0, dev_name(&pdev->dev), mci);
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if (res < 0) {
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edac_mc_printk(mci, KERN_ERR,
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"Unable to request irq %d\n", irq);
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res = -ENODEV;
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goto err2;
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}
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if (regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
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(DRAMINTR_INTRCLR | DRAMINTR_INTREN))) {
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edac_mc_printk(mci, KERN_ERR,
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"Error enabling SDRAM ECC IRQ\n");
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res = -ENODEV;
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goto err2;
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}
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altr_sdr_mc_create_debugfs_nodes(mci);
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devres_close_group(&pdev->dev, NULL);
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return 0;
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err2:
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edac_mc_del_mc(&pdev->dev);
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err:
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devres_release_group(&pdev->dev, NULL);
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free:
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edac_mc_free(mci);
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edac_printk(KERN_ERR, EDAC_MC,
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"EDAC Probe Failed; Error %d\n", res);
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return res;
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}
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static int altr_sdram_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
|
||||
|
||||
static struct platform_driver altr_sdram_edac_driver = {
|
||||
.probe = altr_sdram_probe,
|
||||
.remove = altr_sdram_remove,
|
||||
.driver = {
|
||||
.name = "altr_sdram_edac",
|
||||
.of_match_table = altr_sdram_ctrl_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(altr_sdram_edac_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Thor Thayer");
|
||||
MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");
|
||||
Loading…
Reference in New Issue