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arm64: dts: renesas: rzg2: Add reset control properties for display
Add reset control properties to the device nodes for the Display Units on all supported RZ/G2 SoCs. Note that on these SoCs, there is only a single reset for each pair of DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200218133019.22299-5-geert+renesas@glider.be
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@ -2634,10 +2634,11 @@ du: display@feb00000 {
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>;
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clock-names = "du.0", "du.1", "du.2";
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resets = <&cpg 724>, <&cpg 722>;
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reset-names = "du.0", "du.2";
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status = "disabled";
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renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
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@ -2480,10 +2480,11 @@ du: display@feb00000 {
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 721>;
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clock-names = "du.0", "du.1", "du.3";
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resets = <&cpg 724>, <&cpg 722>;
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reset-names = "du.0", "du.3";
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status = "disabled";
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renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
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@ -1810,9 +1810,10 @@ du: display@feb00000 {
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reg = <0 0xfeb00000 0 0x40000>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>;
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
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clock-names = "du.0", "du.1";
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resets = <&cpg 724>;
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reset-names = "du.0";
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renesas,vsps = <&vspd0 0>, <&vspd1 0>;
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status = "disabled";
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