mirror of https://gitee.com/openkylin/linux.git
drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2)
Just pull the info out of the CRTC state structure rather than staging it in an additional structure. Note that we use cstate->active rather than intel_crtc->active which may appear to be a change in behavior. However since we're no longer trying to recalculate watermarks during the "pipe off" stage of a modeset, intel_crtc->active and cstate->active should always be identical when watermarks are calculated (at least for ILK-style platforms). v2: Clarify reasoning for cstate->active and add a WARN_ON to the code to assert that it really is always identical to intel_crtc->active as expected. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
43d59eda1f
commit
7221fc333d
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@ -1773,12 +1773,6 @@ struct skl_pipe_wm_parameters {
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struct intel_plane_wm_parameters cursor;
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struct intel_plane_wm_parameters cursor;
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};
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};
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struct ilk_pipe_wm_parameters {
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bool active;
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uint32_t pipe_htotal;
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uint32_t pixel_rate;
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};
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struct ilk_wm_maximums {
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struct ilk_wm_maximums {
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uint16_t pri;
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uint16_t pri;
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uint16_t spr;
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uint16_t spr;
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@ -1797,7 +1791,7 @@ struct intel_wm_config {
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* For both WM_PIPE and WM_LP.
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* For both WM_PIPE and WM_LP.
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* mem_value must be in 0.1us units.
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* mem_value must be in 0.1us units.
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*/
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*/
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static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
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static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate,
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const struct intel_plane_state *pstate,
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uint32_t mem_value,
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uint32_t mem_value,
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bool is_lp)
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bool is_lp)
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@ -1805,16 +1799,16 @@ static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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uint32_t method1, method2;
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uint32_t method1, method2;
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if (!params->active || !pstate->visible)
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if (!cstate->base.active || !pstate->visible)
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return 0;
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return 0;
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method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
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method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
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if (!is_lp)
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if (!is_lp)
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return method1;
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return method1;
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method2 = ilk_wm_method2(params->pixel_rate,
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method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
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params->pipe_htotal,
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cstate->base.adjusted_mode.crtc_htotal,
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drm_rect_width(&pstate->dst),
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drm_rect_width(&pstate->dst),
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bpp,
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bpp,
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mem_value);
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mem_value);
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@ -1826,19 +1820,19 @@ static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
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* For both WM_PIPE and WM_LP.
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* For both WM_PIPE and WM_LP.
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* mem_value must be in 0.1us units.
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* mem_value must be in 0.1us units.
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*/
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*/
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static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
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static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate,
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const struct intel_plane_state *pstate,
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uint32_t mem_value)
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uint32_t mem_value)
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{
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{
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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uint32_t method1, method2;
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uint32_t method1, method2;
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if (!params->active || !pstate->visible)
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if (!cstate->base.active || !pstate->visible)
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return 0;
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return 0;
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method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
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method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
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method2 = ilk_wm_method2(params->pixel_rate,
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method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
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params->pipe_htotal,
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cstate->base.adjusted_mode.crtc_htotal,
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drm_rect_width(&pstate->dst),
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drm_rect_width(&pstate->dst),
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bpp,
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bpp,
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mem_value);
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mem_value);
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@ -1849,30 +1843,30 @@ static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
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* For both WM_PIPE and WM_LP.
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* For both WM_PIPE and WM_LP.
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* mem_value must be in 0.1us units.
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* mem_value must be in 0.1us units.
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*/
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*/
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static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
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static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate,
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const struct intel_plane_state *pstate,
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uint32_t mem_value)
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uint32_t mem_value)
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{
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{
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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if (!params->active || !pstate->visible)
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if (!cstate->base.active || !pstate->visible)
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return 0;
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return 0;
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return ilk_wm_method2(params->pixel_rate,
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return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
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params->pipe_htotal,
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cstate->base.adjusted_mode.crtc_htotal,
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drm_rect_width(&pstate->dst),
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drm_rect_width(&pstate->dst),
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bpp,
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bpp,
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mem_value);
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mem_value);
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}
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}
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/* Only for WM_LP. */
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/* Only for WM_LP. */
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static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
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static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate,
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const struct intel_plane_state *pstate,
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uint32_t pri_val)
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uint32_t pri_val)
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{
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{
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
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if (!params->active || !pstate->visible)
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if (!cstate->base.active || !pstate->visible)
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return 0;
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return 0;
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return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
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return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
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@ -2042,7 +2036,7 @@ static bool ilk_validate_wm_level(int level,
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static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
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static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
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const struct intel_crtc *intel_crtc,
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const struct intel_crtc *intel_crtc,
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int level,
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int level,
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const struct ilk_pipe_wm_parameters *p,
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struct intel_crtc_state *cstate,
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struct intel_wm_level *result)
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struct intel_wm_level *result)
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{
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{
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struct intel_plane *intel_plane;
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struct intel_plane *intel_plane;
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@ -2063,18 +2057,18 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
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switch (intel_plane->base.type) {
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switch (intel_plane->base.type) {
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case DRM_PLANE_TYPE_PRIMARY:
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case DRM_PLANE_TYPE_PRIMARY:
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result->pri_val = ilk_compute_pri_wm(p, pstate,
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result->pri_val = ilk_compute_pri_wm(cstate, pstate,
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pri_latency,
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pri_latency,
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level);
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level);
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result->fbc_val = ilk_compute_fbc_wm(p, pstate,
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result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
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result->pri_val);
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result->pri_val);
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break;
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break;
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case DRM_PLANE_TYPE_OVERLAY:
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case DRM_PLANE_TYPE_OVERLAY:
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result->spr_val = ilk_compute_spr_wm(p, pstate,
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result->spr_val = ilk_compute_spr_wm(cstate, pstate,
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spr_latency);
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spr_latency);
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break;
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break;
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case DRM_PLANE_TYPE_CURSOR:
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case DRM_PLANE_TYPE_CURSOR:
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result->cur_val = ilk_compute_cur_wm(p, pstate,
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result->cur_val = ilk_compute_cur_wm(cstate, pstate,
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cur_latency);
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cur_latency);
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break;
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break;
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}
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}
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@ -2338,19 +2332,6 @@ static void skl_setup_wm_latency(struct drm_device *dev)
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intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
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intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
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}
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}
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static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
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struct ilk_pipe_wm_parameters *p)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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if (!intel_crtc->active)
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return;
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p->active = true;
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p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
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p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
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}
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static void ilk_compute_wm_config(struct drm_device *dev,
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static void ilk_compute_wm_config(struct drm_device *dev,
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struct intel_wm_config *config)
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struct intel_wm_config *config)
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{
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{
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@ -2370,10 +2351,10 @@ static void ilk_compute_wm_config(struct drm_device *dev,
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}
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}
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/* Compute new watermarks for the pipe */
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/* Compute new watermarks for the pipe */
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static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
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static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
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const struct ilk_pipe_wm_parameters *params,
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struct intel_pipe_wm *pipe_wm)
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struct intel_pipe_wm *pipe_wm)
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{
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{
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struct drm_crtc *crtc = cstate->base.crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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const struct drm_i915_private *dev_priv = dev->dev_private;
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const struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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@ -2398,8 +2379,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
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(drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
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(drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
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drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
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drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
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pipe_wm->pipe_enabled = cstate->base.active;
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pipe_wm->pipe_enabled = params->active;
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pipe_wm->sprites_enabled = sprstate->visible;
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pipe_wm->sprites_enabled = sprstate->visible;
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pipe_wm->sprites_scaled = config.sprites_scaled;
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pipe_wm->sprites_scaled = config.sprites_scaled;
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@ -2411,7 +2391,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
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if (config.sprites_scaled)
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if (config.sprites_scaled)
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max_level = 0;
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max_level = 0;
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ilk_compute_wm_level(dev_priv, intel_crtc, 0, params, &pipe_wm->wm[0]);
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ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
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pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
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@ -2428,7 +2408,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
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for (level = 1; level <= max_level; level++) {
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for (level = 1; level <= max_level; level++) {
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struct intel_wm_level wm = {};
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struct intel_wm_level wm = {};
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ilk_compute_wm_level(dev_priv, intel_crtc, level, params, &wm);
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ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
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/*
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/*
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* Disable any watermark level that exceeds the
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* Disable any watermark level that exceeds the
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@ -3759,19 +3739,19 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
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static void ilk_update_wm(struct drm_crtc *crtc)
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static void ilk_update_wm(struct drm_crtc *crtc)
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{
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct ilk_wm_maximums max;
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struct ilk_wm_maximums max;
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struct ilk_pipe_wm_parameters params = {};
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struct ilk_wm_values results = {};
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struct ilk_wm_values results = {};
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enum intel_ddb_partitioning partitioning;
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enum intel_ddb_partitioning partitioning;
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struct intel_pipe_wm pipe_wm = {};
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struct intel_pipe_wm pipe_wm = {};
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struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
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struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
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struct intel_wm_config config = {};
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struct intel_wm_config config = {};
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ilk_compute_wm_parameters(crtc, ¶ms);
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WARN_ON(cstate->base.active != intel_crtc->active);
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intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
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intel_compute_pipe_wm(cstate, &pipe_wm);
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if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
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if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
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return;
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return;
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@ -3811,12 +3791,6 @@ ilk_update_sprite_wm(struct drm_plane *plane,
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struct drm_device *dev = plane->dev;
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struct drm_device *dev = plane->dev;
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struct intel_plane *intel_plane = to_intel_plane(plane);
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struct intel_plane *intel_plane = to_intel_plane(plane);
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intel_plane->wm.enabled = enabled;
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intel_plane->wm.scaled = scaled;
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intel_plane->wm.horiz_pixels = sprite_width;
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intel_plane->wm.vert_pixels = sprite_width;
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intel_plane->wm.bytes_per_pixel = pixel_size;
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/*
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/*
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* IVB workaround: must disable low power watermarks for at least
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* IVB workaround: must disable low power watermarks for at least
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* one frame before enabling scaling. LP watermarks can be re-enabled
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* one frame before enabling scaling. LP watermarks can be re-enabled
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