mirror of https://gitee.com/openkylin/linux.git
clk: Fixup spacing in comments
- Remove spaces in front of TABs, - Correct indentation for some CLK_* flag descriptions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Geert Uytterhoeven
Mike Turquette
parent
e07b2b59c9
commit
725b418b43
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@ -40,14 +40,14 @@ struct dentry;
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* through the clk_* api.
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*
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* @prepare: Prepare the clock for enabling. This must not return until
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* the clock is fully prepared, and it's safe to call clk_enable.
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* This callback is intended to allow clock implementations to
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* do any initialisation that may sleep. Called with
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* prepare_lock held.
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* the clock is fully prepared, and it's safe to call clk_enable.
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* This callback is intended to allow clock implementations to
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* do any initialisation that may sleep. Called with
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* prepare_lock held.
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*
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* @unprepare: Release the clock from its prepared state. This will typically
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* undo any work done in the @prepare callback. Called with
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* prepare_lock held.
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* undo any work done in the @prepare callback. Called with
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* prepare_lock held.
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*
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* @is_prepared: Queries the hardware to determine if the clock is prepared.
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* This function is allowed to sleep. Optional, if this op is not
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@ -58,16 +58,16 @@ struct dentry;
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* Called with prepare mutex held. This function may sleep.
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*
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* @enable: Enable the clock atomically. This must not return until the
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* clock is generating a valid clock signal, usable by consumer
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* devices. Called with enable_lock held. This function must not
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* sleep.
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* clock is generating a valid clock signal, usable by consumer
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* devices. Called with enable_lock held. This function must not
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* sleep.
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*
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* @disable: Disable the clock atomically. Called with enable_lock held.
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* This function must not sleep.
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* This function must not sleep.
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*
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* @is_enabled: Queries the hardware to determine if the clock is enabled.
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* This function must not sleep. Optional, if this op is not
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* set then the enable count will be used.
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* This function must not sleep. Optional, if this op is not
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* set then the enable count will be used.
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*
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* @disable_unused: Disable the clock atomically. Only called from
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* clk_disable_unused for gate clocks with special needs.
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@ -75,34 +75,34 @@ struct dentry;
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* sleep.
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*
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* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
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* parent rate is an input parameter. It is up to the caller to
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* ensure that the prepare_mutex is held across this call.
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* Returns the calculated rate. Optional, but recommended - if
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* this op is not set then clock rate will be initialized to 0.
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* parent rate is an input parameter. It is up to the caller to
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* ensure that the prepare_mutex is held across this call.
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* Returns the calculated rate. Optional, but recommended - if
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* this op is not set then clock rate will be initialized to 0.
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*
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* @round_rate: Given a target rate as input, returns the closest rate actually
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* supported by the clock.
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* supported by the clock.
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*
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* @determine_rate: Given a target rate as input, returns the closest rate
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* actually supported by the clock, and optionally the parent clock
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* that should be used to provide the clock rate.
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*
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* @get_parent: Queries the hardware to determine the parent of a clock. The
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* return value is a u8 which specifies the index corresponding to
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* the parent clock. This index can be applied to either the
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* .parent_names or .parents arrays. In short, this function
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* translates the parent value read from hardware into an array
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* index. Currently only called when the clock is initialized by
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* __clk_init. This callback is mandatory for clocks with
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* multiple parents. It is optional (and unnecessary) for clocks
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* with 0 or 1 parents.
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* return value is a u8 which specifies the index corresponding to
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* the parent clock. This index can be applied to either the
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* .parent_names or .parents arrays. In short, this function
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* translates the parent value read from hardware into an array
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* index. Currently only called when the clock is initialized by
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* __clk_init. This callback is mandatory for clocks with
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* multiple parents. It is optional (and unnecessary) for clocks
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* with 0 or 1 parents.
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*
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* @set_parent: Change the input source of this clock; for clocks with multiple
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* possible parents specify a new parent by passing in the index
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* as a u8 corresponding to the parent in either the .parent_names
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* or .parents arrays. This function in affect translates an
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* array index into the value programmed into the hardware.
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* Returns 0 on success, -EERROR otherwise.
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* possible parents specify a new parent by passing in the index
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* as a u8 corresponding to the parent in either the .parent_names
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* or .parents arrays. This function in affect translates an
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* array index into the value programmed into the hardware.
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* Returns 0 on success, -EERROR otherwise.
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*
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* @set_rate: Change the rate of this clock. The requested rate is specified
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* by the second argument, which should typically be the return
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@ -254,12 +254,12 @@ void of_fixed_clk_setup(struct device_node *np);
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*
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* Flags:
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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*/
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struct clk_gate {
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struct clk_hw hw;
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@ -298,20 +298,20 @@ struct clk_div_table {
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*
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* Flags:
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* the raw value read from the register, with the value of zero considered
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* the raw value read from the register, with the value of zero considered
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* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
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* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
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* the hardware register
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* the hardware register
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* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
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* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
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* of this register, and mask of divider bits are in higher 16-bit of this
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* register. While setting the divider bits, higher 16-bit should also be
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* updated to indicate changing divider bits.
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* of this register, and mask of divider bits are in higher 16-bit of this
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* register. While setting the divider bits, higher 16-bit should also be
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* updated to indicate changing divider bits.
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* CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
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* to the closest integer instead of the up one.
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*/
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@ -359,9 +359,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
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* CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
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* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
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* register, and mask of mux bits are in higher 16-bit of this register.
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* While setting the mux bits, higher 16-bit should also be updated to
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* indicate changing mux bits.
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* register, and mask of mux bits are in higher 16-bit of this register.
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* While setting the mux bits, higher 16-bit should also be updated to
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* indicate changing mux bits.
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*/
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struct clk_mux {
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struct clk_hw hw;
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