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drm/amdgpu: remove unnecessary check for mem train 

a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2020-05-22 14:42:35 +08:00 committed by Alex Deucher
parent 0a4fa83c2a
commit 72d208c23c
5 changed files with 7 additions and 58 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -652,10 +652,6 @@ struct amdgpu_fw_vram_usage {
u64 size;
struct amdgpu_bo *reserved_bo;
void *va;
/* GDDR6 training support flag.
*/
bool mem_train_support;
};
/*

5
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
View File

@ -2022,11 +2022,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
if (adev->is_atom_fw) {
amdgpu_atomfirmware_scratch_regs_init(adev);
amdgpu_atomfirmware_allocate_fb_scratch(adev);
ret = amdgpu_atomfirmware_get_mem_train_info(adev);
if (ret) {
DRM_ERROR("Failed to get mem train fb location.\n");
return ret;
}
} else {
amdgpu_atombios_scratch_regs_init(adev);
amdgpu_atombios_allocate_fb_scratch(adev);

47
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
View File

@ -516,7 +516,7 @@ static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
return false;
}
static int gddr6_mem_train_support(struct amdgpu_device *adev)
int amdgpu_mem_train_support(struct amdgpu_device *adev)
{
int ret;
uint32_t major, minor, revision, hw_v;
@ -551,51 +551,6 @@ static int gddr6_mem_train_support(struct amdgpu_device *adev)
return ret;
}
int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
{
struct atom_context *ctx = adev->mode_info.atom_context;
int index;
uint8_t frev, crev;
uint16_t data_offset, size;
int ret;
adev->fw_vram_usage.mem_train_support = false;
if (adev->asic_type != CHIP_NAVI10 &&
adev->asic_type != CHIP_NAVI14 &&
adev->asic_type != CHIP_SIENNA_CICHLID)
return 0;
if (amdgpu_sriov_vf(adev))
return 0;
ret = gddr6_mem_train_support(adev);
if (ret == -1)
return -EINVAL;
else if (ret == 0)
return 0;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
ret = amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev,
&data_offset);
if (ret == 0) {
DRM_ERROR("parse data header failed.\n");
return -EINVAL;
}
DRM_DEBUG("atom firmware common table header size:0x%04x, frev:0x%02x,"
" crev:0x%02x, data_offset:0x%04x.\n", size, frev, crev, data_offset);
/* only support 2.1+ */
if (((uint16_t)frev << 8 | crev) < 0x0201) {
DRM_ERROR("frev:0x%02x, crev:0x%02x < 2.1 !\n", frev, crev);
return -EINVAL;
}
adev->fw_vram_usage.mem_train_support = true;
return 0;
}
int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
{
struct atom_context *ctx = adev->mode_info.atom_context;

2
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
View File

@ -31,11 +31,11 @@ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
int *vram_width, int *vram_type, int *vram_vendor);
int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev);
int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev);
int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev);
int amdgpu_mem_train_support(struct amdgpu_device *adev);
#endif

7
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -1860,10 +1860,13 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
bool mem_train_support = false;
if (!amdgpu_sriov_vf(adev)) {
if (adev->fw_vram_usage.mem_train_support) {
ret = amdgpu_mem_train_support(adev);
if (ret == 1) {
mem_train_support = true;
amdgpu_ttm_training_data_block_init(adev);
} else
} else if (ret == -1)
return -EINVAL;
else
DRM_DEBUG("memory training does not support!\n");
}