From 7318d0f395545089bcf0bbfda61d96fe9c940cd7 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 12 Oct 2017 15:30:19 +0200 Subject: [PATCH] ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD source. If this mux is allowed to propagate rate changes to its parent, setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD panel, will cause the pll3_pfd1_540m PFD to be switched away from its nominal rate to 288 MHz. This has no negative side effects, as there are no other children to this PFD. Still, to avoid surprises, it might be preferrable to switch to the designated video PLL (pll5_video_div) as clock source for the LCDIF pixel clock. Signed-off-by: Philipp Zabel Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-14x14-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 9c23e017d86a..e5d3ef88be60 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -147,6 +147,8 @@ ethphy1: ethernet-phy@1 { &lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;