mirror of https://gitee.com/openkylin/linux.git
x86: use cpuinfo to check for interrupt pending message msr
Simplify code: no need to do a cpuid(1) again. The cpuinfo structure has all necessary information already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -25,35 +25,24 @@ extern void vide(void);
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__asm__(".align 4\nvide: ret");
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#ifdef CONFIG_X86_LOCAL_APIC
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK) {
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if (smp_processor_id() != boot_cpu_physical_apicid)
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printk(KERN_INFO "AMD C1E detected late. "
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" Force timer broadcast.\n");
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return 1;
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}
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break;
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default:
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/* err on the side of caution */
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if (c->x86 < 0x0F)
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return 0;
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/* Family 0x0f models < rev F do not have this MSR */
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if (c->x86 == 0x0f && c->x86_model < 0x40)
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return 0;
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK) {
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if (smp_processor_id() != boot_cpu_physical_apicid)
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printk(KERN_INFO "AMD C1E detected late. "
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"Force timer broadcast.\n");
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return 1;
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}
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return 0;
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@ -297,7 +286,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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if (amd_apic_timer_broken())
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if (amd_apic_timer_broken(c))
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local_apic_timer_disabled = 1;
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#endif
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@ -110,31 +110,23 @@ static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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#endif
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}
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c)
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{
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u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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u32 lo, hi;
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK)
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return 1;
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break;
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default:
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/* err on the side of caution */
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if (c->x86 < 0x0F)
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return 0;
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/* Family 0x0f models < rev F do not have this MSR */
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if (c->x86 == 0x0f && c->x86_model < 0x40)
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return 0;
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK) {
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if (smp_processor_id() != boot_cpu_physical_apicid)
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printk(KERN_INFO "AMD C1E detected late. "
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"Force timer broadcast.\n");
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return 1;
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}
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return 0;
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@ -220,7 +212,7 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (c->x86 == 0x10)
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amd_enable_pci_ext_cfg(c);
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if (amd_apic_timer_broken())
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if (amd_apic_timer_broken(c))
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disable_apic_timer = 1;
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if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
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