mirror of https://gitee.com/openkylin/linux.git
Merge branch 'perf/urgent' into perf/core
Conflicts: tools/perf/builtin-record.c tools/perf/builtin-top.c tools/perf/perf.h tools/perf/util/top.h Merge reason: resolve these cherry-picking conflicts. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
commit
737f24bda7
|
|
@ -17,11 +17,11 @@ reports supported by a device are also provided by sysfs in
|
|||
class/input/event*/device/capabilities/, and the properties of a device are
|
||||
provided in class/input/event*/device/properties.
|
||||
|
||||
Types:
|
||||
==========
|
||||
Types are groupings of codes under a logical input construct. Each type has a
|
||||
set of applicable codes to be used in generating events. See the Codes section
|
||||
for details on valid codes for each type.
|
||||
Event types:
|
||||
===========
|
||||
Event types are groupings of codes under a logical input construct. Each
|
||||
type has a set of applicable codes to be used in generating events. See the
|
||||
Codes section for details on valid codes for each type.
|
||||
|
||||
* EV_SYN:
|
||||
- Used as markers to separate events. Events may be separated in time or in
|
||||
|
|
@ -63,9 +63,9 @@ for details on valid codes for each type.
|
|||
* EV_FF_STATUS:
|
||||
- Used to receive force feedback device status.
|
||||
|
||||
Codes:
|
||||
==========
|
||||
Codes define the precise type of event.
|
||||
Event codes:
|
||||
===========
|
||||
Event codes define the precise type of event.
|
||||
|
||||
EV_SYN:
|
||||
----------
|
||||
|
|
@ -220,6 +220,56 @@ EV_PWR:
|
|||
EV_PWR events are a special type of event used specifically for power
|
||||
mangement. Its usage is not well defined. To be addressed later.
|
||||
|
||||
Device properties:
|
||||
=================
|
||||
Normally, userspace sets up an input device based on the data it emits,
|
||||
i.e., the event types. In the case of two devices emitting the same event
|
||||
types, additional information can be provided in the form of device
|
||||
properties.
|
||||
|
||||
INPUT_PROP_DIRECT + INPUT_PROP_POINTER:
|
||||
--------------------------------------
|
||||
The INPUT_PROP_DIRECT property indicates that device coordinates should be
|
||||
directly mapped to screen coordinates (not taking into account trivial
|
||||
transformations, such as scaling, flipping and rotating). Non-direct input
|
||||
devices require non-trivial transformation, such as absolute to relative
|
||||
transformation for touchpads. Typical direct input devices: touchscreens,
|
||||
drawing tablets; non-direct devices: touchpads, mice.
|
||||
|
||||
The INPUT_PROP_POINTER property indicates that the device is not transposed
|
||||
on the screen and thus requires use of an on-screen pointer to trace user's
|
||||
movements. Typical pointer devices: touchpads, tablets, mice; non-pointer
|
||||
device: touchscreen.
|
||||
|
||||
If neither INPUT_PROP_DIRECT or INPUT_PROP_POINTER are set, the property is
|
||||
considered undefined and the device type should be deduced in the
|
||||
traditional way, using emitted event types.
|
||||
|
||||
INPUT_PROP_BUTTONPAD:
|
||||
--------------------
|
||||
For touchpads where the button is placed beneath the surface, such that
|
||||
pressing down on the pad causes a button click, this property should be
|
||||
set. Common in clickpad notebooks and macbooks from 2009 and onwards.
|
||||
|
||||
Originally, the buttonpad property was coded into the bcm5974 driver
|
||||
version field under the name integrated button. For backwards
|
||||
compatibility, both methods need to be checked in userspace.
|
||||
|
||||
INPUT_PROP_SEMI_MT:
|
||||
------------------
|
||||
Some touchpads, most common between 2008 and 2011, can detect the presence
|
||||
of multiple contacts without resolving the individual positions; only the
|
||||
number of contacts and a rectangular shape is known. For such
|
||||
touchpads, the semi-mt property should be set.
|
||||
|
||||
Depending on the device, the rectangle may enclose all touches, like a
|
||||
bounding box, or just some of them, for instance the two most recent
|
||||
touches. The diversity makes the rectangle of limited use, but some
|
||||
gestures can normally be extracted from it.
|
||||
|
||||
If INPUT_PROP_SEMI_MT is not set, the device is assumed to be a true MT
|
||||
device.
|
||||
|
||||
Guidelines:
|
||||
==========
|
||||
The guidelines below ensure proper single-touch and multi-finger functionality.
|
||||
|
|
@ -240,6 +290,8 @@ used to report when a touch is active on the screen.
|
|||
BTN_{MOUSE,LEFT,MIDDLE,RIGHT} must not be reported as the result of touch
|
||||
contact. BTN_TOOL_<name> events should be reported where possible.
|
||||
|
||||
For new hardware, INPUT_PROP_DIRECT should be set.
|
||||
|
||||
Trackpads:
|
||||
----------
|
||||
Legacy trackpads that only provide relative position information must report
|
||||
|
|
@ -250,6 +302,8 @@ location of the touch. BTN_TOUCH should be used to report when a touch is active
|
|||
on the trackpad. Where multi-finger support is available, BTN_TOOL_<name> should
|
||||
be used to report the number of touches active on the trackpad.
|
||||
|
||||
For new hardware, INPUT_PROP_POINTER should be set.
|
||||
|
||||
Tablets:
|
||||
----------
|
||||
BTN_TOOL_<name> events must be reported when a stylus or other tool is active on
|
||||
|
|
@ -260,3 +314,5 @@ button may be used for buttons on the tablet except BTN_{MOUSE,LEFT}.
|
|||
BTN_{0,1,2,etc} are good generic codes for unlabeled buttons. Do not use
|
||||
meaningful buttons, like BTN_FORWARD, unless the button is labeled for that
|
||||
purpose on the device.
|
||||
|
||||
For new hardware, both INPUT_PROP_DIRECT and INPUT_PROP_POINTER should be set.
|
||||
|
|
|
|||
|
|
@ -601,6 +601,8 @@ can be ORed together:
|
|||
instead of using the one provided by the hardware.
|
||||
512 - A kernel warning has occurred.
|
||||
1024 - A module from drivers/staging was loaded.
|
||||
2048 - The system is working around a severe firmware bug.
|
||||
4096 - An out-of-tree module has been loaded.
|
||||
|
||||
==============================================================
|
||||
|
||||
|
|
|
|||
40
MAINTAINERS
40
MAINTAINERS
|
|
@ -269,7 +269,6 @@ S: Orphan
|
|||
F: drivers/platform/x86/wmi.c
|
||||
|
||||
AD1889 ALSA SOUND DRIVER
|
||||
M: Kyle McMartin <kyle@mcmartin.ca>
|
||||
M: Thibaut Varene <T-Bone@parisc-linux.org>
|
||||
W: http://wiki.parisc-linux.org/AD1889
|
||||
L: linux-parisc@vger.kernel.org
|
||||
|
|
@ -789,12 +788,6 @@ F: arch/arm/mach-mx*/
|
|||
F: arch/arm/mach-imx/
|
||||
F: arch/arm/plat-mxc/
|
||||
|
||||
ARM/FREESCALE IMX51
|
||||
M: Amit Kucheria <amit.kucheria@canonical.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-mx5/
|
||||
|
||||
ARM/FREESCALE IMX6
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -2287,7 +2280,7 @@ F: drivers/acpi/dock.c
|
|||
DOCUMENTATION
|
||||
M: Randy Dunlap <rdunlap@xenotime.net>
|
||||
L: linux-doc@vger.kernel.org
|
||||
T: quilt http://userweb.kernel.org/~rdunlap/kernel-doc-patches/current/
|
||||
T: quilt http://xenotime.net/kernel-doc-patches/current/
|
||||
S: Maintained
|
||||
F: Documentation/
|
||||
|
||||
|
|
@ -3053,7 +3046,6 @@ F: drivers/hwspinlock/hwspinlock_*
|
|||
F: include/linux/hwspinlock.h
|
||||
|
||||
HARMONY SOUND DRIVER
|
||||
M: Kyle McMartin <kyle@mcmartin.ca>
|
||||
L: linux-parisc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: sound/parisc/harmony.*
|
||||
|
|
@ -3324,6 +3316,12 @@ S: Maintained
|
|||
F: net/ieee802154/
|
||||
F: drivers/ieee802154/
|
||||
|
||||
IIO SUBSYSTEM AND DRIVERS
|
||||
M: Jonathan Cameron <jic23@cam.ac.uk>
|
||||
L: linux-iio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/staging/iio/
|
||||
|
||||
IKANOS/ADI EAGLE ADSL USB DRIVER
|
||||
M: Matthieu Castet <castet.matthieu@free.fr>
|
||||
M: Stanislaw Gruszka <stf_xl@wp.pl>
|
||||
|
|
@ -3782,7 +3780,7 @@ F: Documentation/kdump/
|
|||
|
||||
KERNEL AUTOMOUNTER v4 (AUTOFS4)
|
||||
M: Ian Kent <raven@themaw.net>
|
||||
L: autofs@linux.kernel.org
|
||||
L: autofs@vger.kernel.org
|
||||
S: Maintained
|
||||
F: fs/autofs4/
|
||||
|
||||
|
|
@ -3992,11 +3990,11 @@ M: Rusty Russell <rusty@rustcorp.com.au>
|
|||
L: lguest@lists.ozlabs.org
|
||||
W: http://lguest.ozlabs.org/
|
||||
S: Odd Fixes
|
||||
F: Documentation/virtual/lguest/
|
||||
F: arch/x86/include/asm/lguest*.h
|
||||
F: arch/x86/lguest/
|
||||
F: drivers/lguest/
|
||||
F: include/linux/lguest*.h
|
||||
F: arch/x86/include/asm/lguest*.h
|
||||
F: tools/lguest/
|
||||
|
||||
LINUX FOR IBM pSERIES (RS/6000)
|
||||
M: Paul Mackerras <paulus@au.ibm.com>
|
||||
|
|
@ -4136,7 +4134,7 @@ L: linux-ntfs-dev@lists.sourceforge.net
|
|||
W: http://www.linux-ntfs.org/content/view/19/37/
|
||||
S: Maintained
|
||||
F: Documentation/ldm.txt
|
||||
F: fs/partitions/ldm.*
|
||||
F: block/partitions/ldm.*
|
||||
|
||||
LogFS
|
||||
M: Joern Engel <joern@logfs.org>
|
||||
|
|
@ -4687,7 +4685,7 @@ NTFS FILESYSTEM
|
|||
M: Anton Altaparmakov <anton@tuxera.com>
|
||||
L: linux-ntfs-dev@lists.sourceforge.net
|
||||
W: http://www.tuxera.com/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs.git
|
||||
S: Supported
|
||||
F: Documentation/filesystems/ntfs.txt
|
||||
F: fs/ntfs/
|
||||
|
|
@ -5000,9 +4998,8 @@ F: Documentation/blockdev/paride.txt
|
|||
F: drivers/block/paride/
|
||||
|
||||
PARISC ARCHITECTURE
|
||||
M: Kyle McMartin <kyle@mcmartin.ca>
|
||||
M: Helge Deller <deller@gmx.de>
|
||||
M: "James E.J. Bottomley" <jejb@parisc-linux.org>
|
||||
M: Helge Deller <deller@gmx.de>
|
||||
L: linux-parisc@vger.kernel.org
|
||||
W: http://www.parisc-linux.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-parisc/list/
|
||||
|
|
@ -5633,7 +5630,7 @@ W: http://www.ibm.com/developerworks/linux/linux390/
|
|||
S: Supported
|
||||
F: arch/s390/
|
||||
F: drivers/s390/
|
||||
F: fs/partitions/ibm.c
|
||||
F: block/partitions/ibm.c
|
||||
F: Documentation/s390/
|
||||
F: Documentation/DocBook/s390*
|
||||
|
||||
|
|
@ -5861,7 +5858,7 @@ S: Maintained
|
|||
F: drivers/mmc/host/sdhci-spear.c
|
||||
|
||||
SECURITY SUBSYSTEM
|
||||
M: James Morris <jmorris@namei.org>
|
||||
M: James Morris <james.l.morris@oracle.com>
|
||||
L: linux-security-module@vger.kernel.org (suggested Cc:)
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git
|
||||
W: http://security.wiki.kernel.org/
|
||||
|
|
@ -5874,7 +5871,7 @@ S: Supported
|
|||
|
||||
SELINUX SECURITY MODULE
|
||||
M: Stephen Smalley <sds@tycho.nsa.gov>
|
||||
M: James Morris <jmorris@namei.org>
|
||||
M: James Morris <james.l.morris@oracle.com>
|
||||
M: Eric Paris <eparis@parisplace.org>
|
||||
L: selinux@tycho.nsa.gov (subscribers-only, general discussion)
|
||||
W: http://selinuxproject.org
|
||||
|
|
@ -6396,11 +6393,6 @@ M: Omar Ramirez Luna <omar.ramirez@ti.com>
|
|||
S: Odd Fixes
|
||||
F: drivers/staging/tidspbridge/
|
||||
|
||||
STAGING - TRIDENT TVMASTER TMxxxx USB VIDEO CAPTURE DRIVERS
|
||||
L: linux-media@vger.kernel.org
|
||||
S: Odd Fixes
|
||||
F: drivers/staging/tm6000/
|
||||
|
||||
STAGING - USB ENE SM/MS CARD READER DRIVER
|
||||
M: Al Cho <acho@novell.com>
|
||||
S: Odd Fixes
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 3
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ gic:interrupt-controller@10490000 {
|
|||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
cpu-offset = <0x8000>;
|
||||
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -46,11 +46,11 @@ serial@70006040 {
|
|||
};
|
||||
|
||||
serial@70006200 {
|
||||
status = "disable";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
clock-frequency = <216000000>;
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
serial@70006400 {
|
||||
|
|
@ -60,7 +60,7 @@ serial@70006400 {
|
|||
sdhci@c8000000 {
|
||||
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 169 0>; /* gpio PV1 */
|
||||
};
|
||||
|
||||
sdhci@c8000200 {
|
||||
|
|
|
|||
|
|
@ -320,13 +320,6 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
|
|||
return -EBUSY;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we set up a device for bus mastering, we need to check the latency
|
||||
* timer as we don't have even crappy BIOSes to set it properly.
|
||||
* The implementation is from arch/i386/pci/i386.c
|
||||
*/
|
||||
unsigned int pcibios_max_latency = 255;
|
||||
|
||||
/* ITE bridge requires setting latency timer to avoid early bus access
|
||||
termination by PCI bus master devices
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
|
|||
struct pl330_thread *thrd = ch_id;
|
||||
struct pl330_dmac *pl330;
|
||||
unsigned long flags;
|
||||
int ret = 0, active = thrd->req_running;
|
||||
int ret = 0, active;
|
||||
|
||||
if (!thrd || thrd->free || thrd->dmac->state == DYING)
|
||||
return -EINVAL;
|
||||
|
||||
pl330 = thrd->dmac;
|
||||
active = thrd->req_running;
|
||||
|
||||
spin_lock_irqsave(&pl330->lock, flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -137,6 +137,11 @@
|
|||
disable_irq
|
||||
.endm
|
||||
|
||||
.macro save_and_disable_irqs_notrace, oldcpsr
|
||||
mrs \oldcpsr, cpsr
|
||||
disable_irq_notrace
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Restore interrupt state previously stored in a register. We don't
|
||||
* guarantee that this will preserve the flags.
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
|
|||
DCCTRL1, /* Bufferable only */
|
||||
DCCTRL2, /* Cacheable, but do not allocate */
|
||||
DCCTRL3, /* Cacheable and bufferable, but do not allocate */
|
||||
DINVALID1 = 8,
|
||||
DINVALID1, /* AWCACHE = 0x1000 */
|
||||
DINVALID2,
|
||||
DCCTRL6, /* Cacheable write-through, allocate on writes only */
|
||||
DCCTRL7, /* Cacheable write-back, allocate on writes only */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <asm/hw_breakpoint.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
|
||||
|
|
|
|||
|
|
@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
|
|||
unsigned long addr)
|
||||
{
|
||||
pgtable_page_dtor(pte);
|
||||
tlb_add_flush(tlb, addr);
|
||||
|
||||
/*
|
||||
* With the classic ARM MMU, a pte page has two corresponding pmd
|
||||
* entries, each covering 1MB.
|
||||
*/
|
||||
addr &= PMD_MASK;
|
||||
tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
|
||||
tlb_add_flush(tlb, addr + SZ_1M);
|
||||
|
||||
tlb_remove_page(tlb, pte);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -790,7 +790,7 @@ __kuser_cmpxchg64: @ 0xffff0f60
|
|||
smp_dmb arm
|
||||
rsbs r0, r3, #0 @ set returned val and C flag
|
||||
ldmfd sp!, {r4, r5, r6, r7}
|
||||
bx lr
|
||||
usr_ret lr
|
||||
|
||||
#elif !defined(CONFIG_SMP)
|
||||
|
||||
|
|
|
|||
|
|
@ -469,6 +469,20 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
},
|
||||
[C(NODE)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
[C(OP_WRITE)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
[C(OP_PREFETCH)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -579,6 +593,20 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
},
|
||||
[C(NODE)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
[C(OP_WRITE)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
[C(OP_PREFETCH)] = {
|
||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/perf_event.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/audit.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/system.h>
|
||||
|
|
@ -699,10 +700,13 @@ static int vfp_set(struct task_struct *target,
|
|||
{
|
||||
int ret;
|
||||
struct thread_info *thread = task_thread_info(target);
|
||||
struct vfp_hard_struct new_vfp = thread->vfpstate.hard;
|
||||
struct vfp_hard_struct new_vfp;
|
||||
const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
|
||||
const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
|
||||
|
||||
vfp_sync_hwstate(thread);
|
||||
new_vfp = thread->vfpstate.hard;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
||||
&new_vfp.fpregs,
|
||||
user_fpregs_offset,
|
||||
|
|
@ -723,9 +727,8 @@ static int vfp_set(struct task_struct *target,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
vfp_sync_hwstate(thread);
|
||||
thread->vfpstate.hard = new_vfp;
|
||||
vfp_flush_hwstate(thread);
|
||||
thread->vfpstate.hard = new_vfp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -902,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request,
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __ARMEB__
|
||||
#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
|
||||
#else
|
||||
#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
|
||||
#endif
|
||||
|
||||
asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
|
||||
{
|
||||
unsigned long ip;
|
||||
|
|
@ -916,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
|
|||
if (!ip)
|
||||
audit_syscall_exit(regs);
|
||||
else
|
||||
audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0,
|
||||
audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
|
||||
regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
|
||||
|
||||
if (!test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
|
|
|
|||
|
|
@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
|||
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
|
|
@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
|||
__get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
|
||||
__get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
|
||||
|
||||
if (!err)
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = {
|
|||
|
||||
static int twd_cpufreq_init(void)
|
||||
{
|
||||
if (!IS_ERR(twd_clk))
|
||||
if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
|
||||
return cpufreq_register_notifier(&twd_cpufreq_nb,
|
||||
CPUFREQ_TRANSITION_NOTIFIER);
|
||||
|
||||
|
|
|
|||
|
|
@ -266,6 +266,7 @@ void die(const char *str, struct pt_regs *regs, int err)
|
|||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
int ret;
|
||||
enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
|
||||
|
||||
oops_enter();
|
||||
|
||||
|
|
@ -273,7 +274,9 @@ void die(const char *str, struct pt_regs *regs, int err)
|
|||
console_verbose();
|
||||
bust_spinlocks(1);
|
||||
if (!user_mode(regs))
|
||||
report_bug(regs->ARM_pc, regs);
|
||||
bug_type = report_bug(regs->ARM_pc, regs);
|
||||
if (bug_type != BUG_TRAP_TYPE_NONE)
|
||||
str = "Oops - BUG";
|
||||
ret = __die(str, err, thread, regs);
|
||||
|
||||
if (regs && kexec_should_crash(thread->task))
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <asm/page.h>
|
||||
|
||||
#define PROC_INFO \
|
||||
. = ALIGN(4); \
|
||||
VMLINUX_SYMBOL(__proc_info_begin) = .; \
|
||||
*(.proc.info.init) \
|
||||
VMLINUX_SYMBOL(__proc_info_end) = .;
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
|
|||
* USB Device (Gadget)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_USB_AT91
|
||||
#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
|
||||
static struct at91_udc_data udc_data;
|
||||
|
||||
static struct resource udc_resources[] = {
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
|
|||
* USB Device (Gadget)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_USB_AT91
|
||||
#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
|
||||
static struct at91_udc_data udc_data;
|
||||
|
||||
static struct resource udc_resources[] = {
|
||||
|
|
@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {}
|
|||
* CF/IDE
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
|
||||
defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
|
||||
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
|
||||
defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
|
||||
|
||||
static struct at91_cf_data cf0_data;
|
||||
|
|
@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
|||
if (data->flags & AT91_CF_TRUE_IDE)
|
||||
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
|
||||
pdev->name = "pata_at91";
|
||||
#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
|
||||
pdev->name = "at91_ide";
|
||||
#else
|
||||
#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
|
||||
#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
|
||||
#endif
|
||||
else
|
||||
pdev->name = "at91_cf";
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
|
|||
* USB Device (Gadget)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_USB_AT91
|
||||
#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
|
||||
static struct at91_udc_data udc_data;
|
||||
|
||||
static struct resource udc_resources[] = {
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
|
|||
* USB Device (Gadget)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_USB_AT91
|
||||
#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
|
||||
static struct at91_udc_data udc_data;
|
||||
|
||||
static struct resource udc_resources[] = {
|
||||
|
|
@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
|
|||
* Compact Flash (PCMCIA or IDE)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
|
||||
defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
|
||||
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
|
||||
defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
|
||||
|
||||
static struct at91_cf_data cf0_data;
|
||||
|
||||
|
|
@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
|||
at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
|
||||
at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
|
||||
|
||||
pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
|
||||
pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
|
||||
platform_device_register(pdev);
|
||||
}
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -18,6 +18,35 @@
|
|||
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sam9_smc_config {
|
||||
/* Setup register */
|
||||
u8 ncs_read_setup;
|
||||
u8 nrd_setup;
|
||||
u8 ncs_write_setup;
|
||||
u8 nwe_setup;
|
||||
|
||||
/* Pulse register */
|
||||
u8 ncs_read_pulse;
|
||||
u8 nrd_pulse;
|
||||
u8 ncs_write_pulse;
|
||||
u8 nwe_pulse;
|
||||
|
||||
/* Cycle register */
|
||||
u16 read_cycle;
|
||||
u16 write_cycle;
|
||||
|
||||
/* Mode register */
|
||||
u32 mode;
|
||||
u8 tdf_cycles:4;
|
||||
};
|
||||
|
||||
extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
|
||||
#endif
|
||||
|
||||
#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
|
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
|
||||
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* linux/arch/arm/mach-at91/sam9_smc.c
|
||||
*
|
||||
* Copyright (C) 2008 Andrew Victor
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -22,7 +23,22 @@
|
|||
|
||||
static void __iomem *smc_base_addr[2];
|
||||
|
||||
static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
|
||||
static void sam9_smc_cs_write_mode(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
__raw_writel(config->mode
|
||||
| AT91_SMC_TDF_(config->tdf_cycles),
|
||||
base + AT91_SMC_MODE);
|
||||
}
|
||||
|
||||
void sam9_smc_write_mode(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
|
||||
static void sam9_smc_cs_configure(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
|
||||
/* Setup register */
|
||||
|
|
@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con
|
|||
base + AT91_SMC_CYCLE);
|
||||
|
||||
/* Mode register */
|
||||
__raw_writel(config->mode
|
||||
| AT91_SMC_TDF_(config->tdf_cycles),
|
||||
base + AT91_SMC_MODE);
|
||||
sam9_smc_cs_write_mode(base, config);
|
||||
}
|
||||
|
||||
void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config)
|
||||
void sam9_smc_configure(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
|
||||
static void sam9_smc_cs_read_mode(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
u32 val = __raw_readl(base + AT91_SMC_MODE);
|
||||
|
||||
config->mode = (val & ~AT91_SMC_NWECYCLE);
|
||||
config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
|
||||
}
|
||||
|
||||
void sam9_smc_read_mode(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
|
||||
static void sam9_smc_cs_read(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Setup register */
|
||||
val = __raw_readl(base + AT91_SMC_SETUP);
|
||||
|
||||
config->nwe_setup = val & AT91_SMC_NWESETUP;
|
||||
config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
|
||||
config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
|
||||
config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
|
||||
|
||||
/* Pulse register */
|
||||
val = __raw_readl(base + AT91_SMC_PULSE);
|
||||
|
||||
config->nwe_setup = val & AT91_SMC_NWEPULSE;
|
||||
config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
|
||||
config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
|
||||
config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
|
||||
|
||||
/* Cycle register */
|
||||
val = __raw_readl(base + AT91_SMC_CYCLE);
|
||||
|
||||
config->write_cycle = val & AT91_SMC_NWECYCLE;
|
||||
config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
|
||||
|
||||
/* Mode register */
|
||||
sam9_smc_cs_read_mode(base, config);
|
||||
}
|
||||
|
||||
void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
|
||||
void __init at91sam9_ioremap_smc(int id, u32 addr)
|
||||
{
|
||||
if (id > 1) {
|
||||
|
|
|
|||
|
|
@ -8,27 +8,4 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
struct sam9_smc_config {
|
||||
/* Setup register */
|
||||
u8 ncs_read_setup;
|
||||
u8 nrd_setup;
|
||||
u8 ncs_write_setup;
|
||||
u8 nwe_setup;
|
||||
|
||||
/* Pulse register */
|
||||
u8 ncs_read_pulse;
|
||||
u8 nrd_pulse;
|
||||
u8 ncs_write_pulse;
|
||||
u8 nwe_pulse;
|
||||
|
||||
/* Cycle register */
|
||||
u16 read_cycle;
|
||||
u16 write_cycle;
|
||||
|
||||
/* Mode register */
|
||||
u32 mode;
|
||||
u8 tdf_cycles:4;
|
||||
};
|
||||
|
||||
extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
|
||||
extern void __init at91sam9_ioremap_smc(int id, u32 addr);
|
||||
|
|
|
|||
|
|
@ -194,6 +194,6 @@ MACHINE_START(BCMRING, "BCMRING")
|
|||
.init_early = bcmring_init_early,
|
||||
.init_irq = bcmring_init_irq,
|
||||
.timer = &bcmring_timer,
|
||||
.init_machine = bcmring_init_machine
|
||||
.init_machine = bcmring_init_machine,
|
||||
.restart = bcmring_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -33,17 +33,11 @@
|
|||
|
||||
#include <mach/timer.h>
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pfn.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/sched.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
|
||||
/* especially since dc4 doesn't use kmalloc'd memory. */
|
||||
|
||||
#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
|
||||
|
||||
/* ---- Public Variables ------------------------------------------------- */
|
||||
|
||||
/* ---- Private Constants and Types -------------------------------------- */
|
||||
|
|
@ -53,58 +47,18 @@
|
|||
#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f)
|
||||
#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f)
|
||||
|
||||
#define DMA_MAP_DEBUG 0
|
||||
|
||||
#if DMA_MAP_DEBUG
|
||||
# define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args)
|
||||
#else
|
||||
# define DMA_MAP_PRINT(fmt, args...)
|
||||
#endif
|
||||
|
||||
/* ---- Private Variables ------------------------------------------------ */
|
||||
|
||||
static DMA_Global_t gDMA;
|
||||
static struct proc_dir_entry *gDmaDir;
|
||||
|
||||
static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
|
||||
static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
|
||||
static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
|
||||
static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
|
||||
|
||||
#include "dma_device.c"
|
||||
|
||||
/* ---- Private Function Prototypes -------------------------------------- */
|
||||
|
||||
/* ---- Functions ------------------------------------------------------- */
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Displays information for /proc/dma/mem-type
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
|
||||
int count, int *eof, void *data)
|
||||
{
|
||||
int len = 0;
|
||||
|
||||
len += sprintf(buf + len, "dma_map_mem statistics\n");
|
||||
len +=
|
||||
sprintf(buf + len, "coherent: %d\n",
|
||||
atomic_read(&gDmaStatMemTypeCoherent));
|
||||
len +=
|
||||
sprintf(buf + len, "kmalloc: %d\n",
|
||||
atomic_read(&gDmaStatMemTypeKmalloc));
|
||||
len +=
|
||||
sprintf(buf + len, "vmalloc: %d\n",
|
||||
atomic_read(&gDmaStatMemTypeVmalloc));
|
||||
len +=
|
||||
sprintf(buf + len, "user: %d\n",
|
||||
atomic_read(&gDmaStatMemTypeUser));
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Displays information for /proc/dma/channels
|
||||
|
|
@ -846,8 +800,6 @@ int dma_init(void)
|
|||
dma_proc_read_channels, NULL);
|
||||
create_proc_read_entry("devices", 0, gDmaDir,
|
||||
dma_proc_read_devices, NULL);
|
||||
create_proc_read_entry("mem-type", 0, gDmaDir,
|
||||
dma_proc_read_mem_type, NULL);
|
||||
}
|
||||
|
||||
out:
|
||||
|
|
@ -1565,767 +1517,3 @@ int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for.
|
|||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_set_device_handler);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Initializes a memory mapping structure
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_init_mem_map(DMA_MemMap_t *memMap)
|
||||
{
|
||||
memset(memMap, 0, sizeof(*memMap));
|
||||
|
||||
sema_init(&memMap->lock, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_init_mem_map);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Releases any memory currently being held by a memory mapping structure.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_term_mem_map(DMA_MemMap_t *memMap)
|
||||
{
|
||||
down(&memMap->lock); /* Just being paranoid */
|
||||
|
||||
/* Free up any allocated memory */
|
||||
|
||||
up(&memMap->lock);
|
||||
memset(memMap, 0, sizeof(*memMap));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_term_mem_map);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Looks at a memory address and categorizes it.
|
||||
*
|
||||
* @return One of the values from the DMA_MemType_t enumeration.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
DMA_MemType_t dma_mem_type(void *addr)
|
||||
{
|
||||
unsigned long addrVal = (unsigned long)addr;
|
||||
|
||||
if (addrVal >= CONSISTENT_BASE) {
|
||||
/* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
|
||||
|
||||
/* dma_alloc_xxx pages are physically and virtually contiguous */
|
||||
|
||||
return DMA_MEM_TYPE_DMA;
|
||||
}
|
||||
|
||||
/* Technically, we could add one more classification. Addresses between VMALLOC_END */
|
||||
/* and the beginning of the DMA virtual address could be considered to be I/O space. */
|
||||
/* Right now, nobody cares about this particular classification, so we ignore it. */
|
||||
|
||||
if (is_vmalloc_addr(addr)) {
|
||||
/* Address comes from the vmalloc'd region. Pages are virtually */
|
||||
/* contiguous but NOT physically contiguous */
|
||||
|
||||
return DMA_MEM_TYPE_VMALLOC;
|
||||
}
|
||||
|
||||
if (addrVal >= PAGE_OFFSET) {
|
||||
/* PAGE_OFFSET is typically 0xC0000000 */
|
||||
|
||||
/* kmalloc'd pages are physically contiguous */
|
||||
|
||||
return DMA_MEM_TYPE_KMALLOC;
|
||||
}
|
||||
|
||||
return DMA_MEM_TYPE_USER;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_mem_type);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Looks at a memory address and determines if we support DMA'ing to/from
|
||||
* that type of memory.
|
||||
*
|
||||
* @return boolean -
|
||||
* return value != 0 means dma supported
|
||||
* return value == 0 means dma not supported
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_mem_supports_dma(void *addr)
|
||||
{
|
||||
DMA_MemType_t memType = dma_mem_type(addr);
|
||||
|
||||
return (memType == DMA_MEM_TYPE_DMA)
|
||||
#if ALLOW_MAP_OF_KMALLOC_MEMORY
|
||||
|| (memType == DMA_MEM_TYPE_KMALLOC)
|
||||
#endif
|
||||
|| (memType == DMA_MEM_TYPE_USER);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_mem_supports_dma);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Maps in a memory region such that it can be used for performing a DMA.
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
enum dma_data_direction dir /* Direction that the mapping will be going */
|
||||
) {
|
||||
int rc;
|
||||
|
||||
down(&memMap->lock);
|
||||
|
||||
DMA_MAP_PRINT("memMap: %p\n", memMap);
|
||||
|
||||
if (memMap->inUse) {
|
||||
printk(KERN_ERR "%s: memory map %p is already being used\n",
|
||||
__func__, memMap);
|
||||
rc = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
memMap->inUse = 1;
|
||||
memMap->dir = dir;
|
||||
memMap->numRegionsUsed = 0;
|
||||
|
||||
rc = 0;
|
||||
|
||||
out:
|
||||
|
||||
DMA_MAP_PRINT("returning %d", rc);
|
||||
|
||||
up(&memMap->lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_map_start);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Adds a segment of memory to a memory map. Each segment is both
|
||||
* physically and virtually contiguous.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
DMA_Region_t *region, /* Region that the segment belongs to */
|
||||
void *virtAddr, /* Virtual address of the segment being added */
|
||||
dma_addr_t physAddr, /* Physical address of the segment being added */
|
||||
size_t numBytes /* Number of bytes of the segment being added */
|
||||
) {
|
||||
DMA_Segment_t *segment;
|
||||
|
||||
DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
|
||||
physAddr, numBytes);
|
||||
|
||||
/* Sanity check */
|
||||
|
||||
if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
|
||||
|| (((unsigned long)virtAddr + numBytes)) >
|
||||
((unsigned long)region->virtAddr + region->numBytes)) {
|
||||
printk(KERN_ERR
|
||||
"%s: virtAddr %p is outside region @ %p len: %d\n",
|
||||
__func__, virtAddr, region->virtAddr, region->numBytes);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (region->numSegmentsUsed > 0) {
|
||||
/* Check to see if this segment is physically contiguous with the previous one */
|
||||
|
||||
segment = ®ion->segment[region->numSegmentsUsed - 1];
|
||||
|
||||
if ((segment->physAddr + segment->numBytes) == physAddr) {
|
||||
/* It is - just add on to the end */
|
||||
|
||||
DMA_MAP_PRINT("appending %d bytes to last segment\n",
|
||||
numBytes);
|
||||
|
||||
segment->numBytes += numBytes;
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reallocate to hold more segments, if required. */
|
||||
|
||||
if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
|
||||
DMA_Segment_t *newSegment;
|
||||
size_t oldSize =
|
||||
region->numSegmentsAllocated * sizeof(*newSegment);
|
||||
int newAlloc = region->numSegmentsAllocated + 4;
|
||||
size_t newSize = newAlloc * sizeof(*newSegment);
|
||||
|
||||
newSegment = kmalloc(newSize, GFP_KERNEL);
|
||||
if (newSegment == NULL) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
memcpy(newSegment, region->segment, oldSize);
|
||||
memset(&((uint8_t *) newSegment)[oldSize], 0,
|
||||
newSize - oldSize);
|
||||
kfree(region->segment);
|
||||
|
||||
region->numSegmentsAllocated = newAlloc;
|
||||
region->segment = newSegment;
|
||||
}
|
||||
|
||||
segment = ®ion->segment[region->numSegmentsUsed];
|
||||
region->numSegmentsUsed++;
|
||||
|
||||
segment->virtAddr = virtAddr;
|
||||
segment->physAddr = physAddr;
|
||||
segment->numBytes = numBytes;
|
||||
|
||||
DMA_MAP_PRINT("returning success\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Adds a region of memory to a memory map. Each region is virtually
|
||||
* contiguous, but not necessarily physically contiguous.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
void *mem, /* Virtual address that we want to get a map of */
|
||||
size_t numBytes /* Number of bytes being mapped */
|
||||
) {
|
||||
unsigned long addr = (unsigned long)mem;
|
||||
unsigned int offset;
|
||||
int rc = 0;
|
||||
DMA_Region_t *region;
|
||||
dma_addr_t physAddr;
|
||||
|
||||
down(&memMap->lock);
|
||||
|
||||
DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
|
||||
|
||||
if (!memMap->inUse) {
|
||||
printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
|
||||
__func__);
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Reallocate to hold more regions. */
|
||||
|
||||
if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
|
||||
DMA_Region_t *newRegion;
|
||||
size_t oldSize =
|
||||
memMap->numRegionsAllocated * sizeof(*newRegion);
|
||||
int newAlloc = memMap->numRegionsAllocated + 4;
|
||||
size_t newSize = newAlloc * sizeof(*newRegion);
|
||||
|
||||
newRegion = kmalloc(newSize, GFP_KERNEL);
|
||||
if (newRegion == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
memcpy(newRegion, memMap->region, oldSize);
|
||||
memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
|
||||
|
||||
kfree(memMap->region);
|
||||
|
||||
memMap->numRegionsAllocated = newAlloc;
|
||||
memMap->region = newRegion;
|
||||
}
|
||||
|
||||
region = &memMap->region[memMap->numRegionsUsed];
|
||||
memMap->numRegionsUsed++;
|
||||
|
||||
offset = addr & ~PAGE_MASK;
|
||||
|
||||
region->memType = dma_mem_type(mem);
|
||||
region->virtAddr = mem;
|
||||
region->numBytes = numBytes;
|
||||
region->numSegmentsUsed = 0;
|
||||
region->numLockedPages = 0;
|
||||
region->lockedPages = NULL;
|
||||
|
||||
switch (region->memType) {
|
||||
case DMA_MEM_TYPE_VMALLOC:
|
||||
{
|
||||
atomic_inc(&gDmaStatMemTypeVmalloc);
|
||||
|
||||
/* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
|
||||
|
||||
/* vmalloc'd pages are not physically contiguous */
|
||||
|
||||
rc = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_KMALLOC:
|
||||
{
|
||||
atomic_inc(&gDmaStatMemTypeKmalloc);
|
||||
|
||||
/* kmalloc'd pages are physically contiguous, so they'll have exactly */
|
||||
/* one segment */
|
||||
|
||||
#if ALLOW_MAP_OF_KMALLOC_MEMORY
|
||||
physAddr =
|
||||
dma_map_single(NULL, mem, numBytes, memMap->dir);
|
||||
rc = dma_map_add_segment(memMap, region, mem, physAddr,
|
||||
numBytes);
|
||||
#else
|
||||
rc = -EINVAL;
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_DMA:
|
||||
{
|
||||
/* dma_alloc_xxx pages are physically contiguous */
|
||||
|
||||
atomic_inc(&gDmaStatMemTypeCoherent);
|
||||
|
||||
physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
|
||||
|
||||
dma_sync_single_for_cpu(NULL, physAddr, numBytes,
|
||||
memMap->dir);
|
||||
rc = dma_map_add_segment(memMap, region, mem, physAddr,
|
||||
numBytes);
|
||||
break;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_USER:
|
||||
{
|
||||
size_t firstPageOffset;
|
||||
size_t firstPageSize;
|
||||
struct page **pages;
|
||||
struct task_struct *userTask;
|
||||
|
||||
atomic_inc(&gDmaStatMemTypeUser);
|
||||
|
||||
#if 1
|
||||
/* If the pages are user pages, then the dma_mem_map_set_user_task function */
|
||||
/* must have been previously called. */
|
||||
|
||||
if (memMap->userTask == NULL) {
|
||||
printk(KERN_ERR
|
||||
"%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* User pages need to be locked. */
|
||||
|
||||
firstPageOffset =
|
||||
(unsigned long)region->virtAddr & (PAGE_SIZE - 1);
|
||||
firstPageSize = PAGE_SIZE - firstPageOffset;
|
||||
|
||||
region->numLockedPages = (firstPageOffset
|
||||
+ region->numBytes +
|
||||
PAGE_SIZE - 1) / PAGE_SIZE;
|
||||
pages =
|
||||
kmalloc(region->numLockedPages *
|
||||
sizeof(struct page *), GFP_KERNEL);
|
||||
|
||||
if (pages == NULL) {
|
||||
region->numLockedPages = 0;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
userTask = memMap->userTask;
|
||||
|
||||
down_read(&userTask->mm->mmap_sem);
|
||||
rc = get_user_pages(userTask, /* task */
|
||||
userTask->mm, /* mm */
|
||||
(unsigned long)region->virtAddr, /* start */
|
||||
region->numLockedPages, /* len */
|
||||
memMap->dir == DMA_FROM_DEVICE, /* write */
|
||||
0, /* force */
|
||||
pages, /* pages (array of pointers to page) */
|
||||
NULL); /* vmas */
|
||||
up_read(&userTask->mm->mmap_sem);
|
||||
|
||||
if (rc != region->numLockedPages) {
|
||||
kfree(pages);
|
||||
region->numLockedPages = 0;
|
||||
|
||||
if (rc >= 0) {
|
||||
rc = -EINVAL;
|
||||
}
|
||||
} else {
|
||||
uint8_t *virtAddr = region->virtAddr;
|
||||
size_t bytesRemaining;
|
||||
int pageIdx;
|
||||
|
||||
rc = 0; /* Since get_user_pages returns +ve number */
|
||||
|
||||
region->lockedPages = pages;
|
||||
|
||||
/* We've locked the user pages. Now we need to walk them and figure */
|
||||
/* out the physical addresses. */
|
||||
|
||||
/* The first page may be partial */
|
||||
|
||||
dma_map_add_segment(memMap,
|
||||
region,
|
||||
virtAddr,
|
||||
PFN_PHYS(page_to_pfn
|
||||
(pages[0])) +
|
||||
firstPageOffset,
|
||||
firstPageSize);
|
||||
|
||||
virtAddr += firstPageSize;
|
||||
bytesRemaining =
|
||||
region->numBytes - firstPageSize;
|
||||
|
||||
for (pageIdx = 1;
|
||||
pageIdx < region->numLockedPages;
|
||||
pageIdx++) {
|
||||
size_t bytesThisPage =
|
||||
(bytesRemaining >
|
||||
PAGE_SIZE ? PAGE_SIZE :
|
||||
bytesRemaining);
|
||||
|
||||
DMA_MAP_PRINT
|
||||
("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
|
||||
pageIdx, pages[pageIdx],
|
||||
page_to_pfn(pages[pageIdx]),
|
||||
PFN_PHYS(page_to_pfn
|
||||
(pages[pageIdx])));
|
||||
|
||||
dma_map_add_segment(memMap,
|
||||
region,
|
||||
virtAddr,
|
||||
PFN_PHYS(page_to_pfn
|
||||
(pages
|
||||
[pageIdx])),
|
||||
bytesThisPage);
|
||||
|
||||
virtAddr += bytesThisPage;
|
||||
bytesRemaining -= bytesThisPage;
|
||||
}
|
||||
}
|
||||
#else
|
||||
printk(KERN_ERR
|
||||
"%s: User mode pages are not yet supported\n",
|
||||
__func__);
|
||||
|
||||
/* user pages are not physically contiguous */
|
||||
|
||||
rc = -EINVAL;
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
printk(KERN_ERR "%s: Unsupported memory type: %d\n",
|
||||
__func__, region->memType);
|
||||
|
||||
rc = -EINVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (rc != 0) {
|
||||
memMap->numRegionsUsed--;
|
||||
}
|
||||
|
||||
out:
|
||||
|
||||
DMA_MAP_PRINT("returning %d\n", rc);
|
||||
|
||||
up(&memMap->lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_map_add_segment);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Maps in a memory region such that it can be used for performing a DMA.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
void *mem, /* Virtual address that we want to get a map of */
|
||||
size_t numBytes, /* Number of bytes being mapped */
|
||||
enum dma_data_direction dir /* Direction that the mapping will be going */
|
||||
) {
|
||||
int rc;
|
||||
|
||||
rc = dma_map_start(memMap, dir);
|
||||
if (rc == 0) {
|
||||
rc = dma_map_add_region(memMap, mem, numBytes);
|
||||
if (rc < 0) {
|
||||
/* Since the add fails, this function will fail, and the caller won't */
|
||||
/* call unmap, so we need to do it here. */
|
||||
|
||||
dma_unmap(memMap, 0);
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_map_mem);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Setup a descriptor ring for a given memory map.
|
||||
*
|
||||
* It is assumed that the descriptor ring has already been initialized, and
|
||||
* this routine will only reallocate a new descriptor ring if the existing
|
||||
* one is too small.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
|
||||
DMA_MemMap_t *memMap, /* Memory map that will be used */
|
||||
dma_addr_t devPhysAddr /* Physical address of device */
|
||||
) {
|
||||
int rc;
|
||||
int numDescriptors;
|
||||
DMA_DeviceAttribute_t *devAttr;
|
||||
DMA_Region_t *region;
|
||||
DMA_Segment_t *segment;
|
||||
dma_addr_t srcPhysAddr;
|
||||
dma_addr_t dstPhysAddr;
|
||||
int regionIdx;
|
||||
int segmentIdx;
|
||||
|
||||
devAttr = &DMA_gDeviceAttribute[dev];
|
||||
|
||||
down(&memMap->lock);
|
||||
|
||||
/* Figure out how many descriptors we need */
|
||||
|
||||
numDescriptors = 0;
|
||||
for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
|
||||
region = &memMap->region[regionIdx];
|
||||
|
||||
for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
|
||||
segmentIdx++) {
|
||||
segment = ®ion->segment[segmentIdx];
|
||||
|
||||
if (memMap->dir == DMA_TO_DEVICE) {
|
||||
srcPhysAddr = segment->physAddr;
|
||||
dstPhysAddr = devPhysAddr;
|
||||
} else {
|
||||
srcPhysAddr = devPhysAddr;
|
||||
dstPhysAddr = segment->physAddr;
|
||||
}
|
||||
|
||||
rc =
|
||||
dma_calculate_descriptor_count(dev, srcPhysAddr,
|
||||
dstPhysAddr,
|
||||
segment->
|
||||
numBytes);
|
||||
if (rc < 0) {
|
||||
printk(KERN_ERR
|
||||
"%s: dma_calculate_descriptor_count failed: %d\n",
|
||||
__func__, rc);
|
||||
goto out;
|
||||
}
|
||||
numDescriptors += rc;
|
||||
}
|
||||
}
|
||||
|
||||
/* Adjust the size of the ring, if it isn't big enough */
|
||||
|
||||
if (numDescriptors > devAttr->ring.descriptorsAllocated) {
|
||||
dma_free_descriptor_ring(&devAttr->ring);
|
||||
rc =
|
||||
dma_alloc_descriptor_ring(&devAttr->ring,
|
||||
numDescriptors);
|
||||
if (rc < 0) {
|
||||
printk(KERN_ERR
|
||||
"%s: dma_alloc_descriptor_ring failed: %d\n",
|
||||
__func__, rc);
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
rc =
|
||||
dma_init_descriptor_ring(&devAttr->ring,
|
||||
numDescriptors);
|
||||
if (rc < 0) {
|
||||
printk(KERN_ERR
|
||||
"%s: dma_init_descriptor_ring failed: %d\n",
|
||||
__func__, rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Populate the descriptors */
|
||||
|
||||
for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
|
||||
region = &memMap->region[regionIdx];
|
||||
|
||||
for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
|
||||
segmentIdx++) {
|
||||
segment = ®ion->segment[segmentIdx];
|
||||
|
||||
if (memMap->dir == DMA_TO_DEVICE) {
|
||||
srcPhysAddr = segment->physAddr;
|
||||
dstPhysAddr = devPhysAddr;
|
||||
} else {
|
||||
srcPhysAddr = devPhysAddr;
|
||||
dstPhysAddr = segment->physAddr;
|
||||
}
|
||||
|
||||
rc =
|
||||
dma_add_descriptors(&devAttr->ring, dev,
|
||||
srcPhysAddr, dstPhysAddr,
|
||||
segment->numBytes);
|
||||
if (rc < 0) {
|
||||
printk(KERN_ERR
|
||||
"%s: dma_add_descriptors failed: %d\n",
|
||||
__func__, rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rc = 0;
|
||||
|
||||
out:
|
||||
|
||||
up(&memMap->lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_map_create_descriptor_ring);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Maps in a memory region such that it can be used for performing a DMA.
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
int dirtied /* non-zero if any of the pages were modified */
|
||||
) {
|
||||
|
||||
int rc = 0;
|
||||
int regionIdx;
|
||||
int segmentIdx;
|
||||
DMA_Region_t *region;
|
||||
DMA_Segment_t *segment;
|
||||
|
||||
down(&memMap->lock);
|
||||
|
||||
for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
|
||||
region = &memMap->region[regionIdx];
|
||||
|
||||
for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
|
||||
segmentIdx++) {
|
||||
segment = ®ion->segment[segmentIdx];
|
||||
|
||||
switch (region->memType) {
|
||||
case DMA_MEM_TYPE_VMALLOC:
|
||||
{
|
||||
printk(KERN_ERR
|
||||
"%s: vmalloc'd pages are not yet supported\n",
|
||||
__func__);
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_KMALLOC:
|
||||
{
|
||||
#if ALLOW_MAP_OF_KMALLOC_MEMORY
|
||||
dma_unmap_single(NULL,
|
||||
segment->physAddr,
|
||||
segment->numBytes,
|
||||
memMap->dir);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_DMA:
|
||||
{
|
||||
dma_sync_single_for_cpu(NULL,
|
||||
segment->
|
||||
physAddr,
|
||||
segment->
|
||||
numBytes,
|
||||
memMap->dir);
|
||||
break;
|
||||
}
|
||||
|
||||
case DMA_MEM_TYPE_USER:
|
||||
{
|
||||
/* Nothing to do here. */
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
printk(KERN_ERR
|
||||
"%s: Unsupported memory type: %d\n",
|
||||
__func__, region->memType);
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
segment->virtAddr = NULL;
|
||||
segment->physAddr = 0;
|
||||
segment->numBytes = 0;
|
||||
}
|
||||
|
||||
if (region->numLockedPages > 0) {
|
||||
int pageIdx;
|
||||
|
||||
/* Some user pages were locked. We need to go and unlock them now. */
|
||||
|
||||
for (pageIdx = 0; pageIdx < region->numLockedPages;
|
||||
pageIdx++) {
|
||||
struct page *page =
|
||||
region->lockedPages[pageIdx];
|
||||
|
||||
if (memMap->dir == DMA_FROM_DEVICE) {
|
||||
SetPageDirty(page);
|
||||
}
|
||||
page_cache_release(page);
|
||||
}
|
||||
kfree(region->lockedPages);
|
||||
region->numLockedPages = 0;
|
||||
region->lockedPages = NULL;
|
||||
}
|
||||
|
||||
region->memType = DMA_MEM_TYPE_NONE;
|
||||
region->virtAddr = NULL;
|
||||
region->numBytes = 0;
|
||||
region->numSegmentsUsed = 0;
|
||||
}
|
||||
memMap->userTask = NULL;
|
||||
memMap->numRegionsUsed = 0;
|
||||
memMap->inUse = 0;
|
||||
|
||||
out:
|
||||
up(&memMap->lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dma_unmap);
|
||||
|
|
|
|||
|
|
@ -26,15 +26,9 @@
|
|||
/* ---- Include Files ---------------------------------------------------- */
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/semaphore.h>
|
||||
#include <csp/dmacHw.h>
|
||||
#include <mach/timer.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/pagemap.h>
|
||||
|
||||
/* ---- Constants and Types ---------------------------------------------- */
|
||||
|
||||
|
|
@ -111,78 +105,6 @@ typedef struct {
|
|||
|
||||
} DMA_DescriptorRing_t;
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
|
||||
* DMA chains from a variety of memory sources.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */
|
||||
/* off not being DMA'd. */
|
||||
|
||||
typedef enum {
|
||||
DMA_MEM_TYPE_NONE, /* Not a valid setting */
|
||||
DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */
|
||||
DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */
|
||||
DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */
|
||||
DMA_MEM_TYPE_USER, /* Memory came from user space. */
|
||||
|
||||
} DMA_MemType_t;
|
||||
|
||||
/* A segment represents a physically and virtually contiguous chunk of memory. */
|
||||
/* i.e. each segment can be DMA'd */
|
||||
/* A user of the DMA code will add memory regions. Each region may need to be */
|
||||
/* represented by one or more segments. */
|
||||
|
||||
typedef struct {
|
||||
void *virtAddr; /* Virtual address used for this segment */
|
||||
dma_addr_t physAddr; /* Physical address this segment maps to */
|
||||
size_t numBytes; /* Size of the segment, in bytes */
|
||||
|
||||
} DMA_Segment_t;
|
||||
|
||||
/* A region represents a virtually contiguous chunk of memory, which may be */
|
||||
/* made up of multiple segments. */
|
||||
|
||||
typedef struct {
|
||||
DMA_MemType_t memType;
|
||||
void *virtAddr;
|
||||
size_t numBytes;
|
||||
|
||||
/* Each region (virtually contiguous) consists of one or more segments. Each */
|
||||
/* segment is virtually and physically contiguous. */
|
||||
|
||||
int numSegmentsUsed;
|
||||
int numSegmentsAllocated;
|
||||
DMA_Segment_t *segment;
|
||||
|
||||
/* When a region corresponds to user memory, we need to lock all of the pages */
|
||||
/* down before we can figure out the physical addresses. The lockedPage array contains */
|
||||
/* the pages that were locked, and which subsequently need to be unlocked once the */
|
||||
/* memory is unmapped. */
|
||||
|
||||
unsigned numLockedPages;
|
||||
struct page **lockedPages;
|
||||
|
||||
} DMA_Region_t;
|
||||
|
||||
typedef struct {
|
||||
int inUse; /* Is this mapping currently being used? */
|
||||
struct semaphore lock; /* Acquired when using this structure */
|
||||
enum dma_data_direction dir; /* Direction this transfer is intended for */
|
||||
|
||||
/* In the event that we're mapping user memory, we need to know which task */
|
||||
/* the memory is for, so that we can obtain the correct mm locks. */
|
||||
|
||||
struct task_struct *userTask;
|
||||
|
||||
int numRegionsUsed;
|
||||
int numRegionsAllocated;
|
||||
DMA_Region_t *region;
|
||||
|
||||
} DMA_MemMap_t;
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* The DMA_DeviceAttribute_t contains information which describes a
|
||||
|
|
@ -568,124 +490,6 @@ int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
|
|||
size_t numBytes /* Number of bytes in each destination buffer */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Initializes a DMA_MemMap_t data structure
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Releases any memory currently being held by a memory mapping structure.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Looks at a memory address and categorizes it.
|
||||
*
|
||||
* @return One of the values from the DMA_MemType_t enumeration.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
DMA_MemType_t dma_mem_type(void *addr);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Sets the process (aka userTask) associated with a mem map. This is
|
||||
* required if user-mode segments will be added to the mapping.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
|
||||
struct task_struct *task)
|
||||
{
|
||||
memMap->userTask = task;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Looks at a memory address and determines if we support DMA'ing to/from
|
||||
* that type of memory.
|
||||
*
|
||||
* @return boolean -
|
||||
* return value != 0 means dma supported
|
||||
* return value == 0 means dma not supported
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_mem_supports_dma(void *addr);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Initializes a memory map for use. Since this function acquires a
|
||||
* sempaphore within the memory map, it is VERY important that dma_unmap
|
||||
* be called when you're finished using the map.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
enum dma_data_direction dir /* Direction that the mapping will be going */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Adds a segment of memory to a memory map.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
void *mem, /* Virtual address that we want to get a map of */
|
||||
size_t numBytes /* Number of bytes being mapped */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Creates a descriptor ring from a memory mapping.
|
||||
*
|
||||
* @return 0 on success, error code otherwise.
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
|
||||
DMA_MemMap_t *memMap, /* Memory map that will be used */
|
||||
dma_addr_t devPhysAddr /* Physical address of device */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Maps in a memory region such that it can be used for performing a DMA.
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
void *addr, /* Virtual address that we want to get a map of */
|
||||
size_t count, /* Number of bytes being mapped */
|
||||
enum dma_data_direction dir /* Direction that the mapping will be going */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Maps in a memory region such that it can be used for performing a DMA.
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
|
||||
int dirtied /* non-zero if any of the pages were modified */
|
||||
);
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Initiates a transfer when the descriptors have already been setup.
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
#include <mach/aemif.h>
|
||||
#include <mach/spi.h>
|
||||
|
||||
#define DA850_EVM_PHY_ID "0:00"
|
||||
#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
|
||||
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
|
||||
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static inline int have_tvp7002(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#define DM365_EVM_PHY_ID "0:01"
|
||||
#define DM365_EVM_PHY_ID "davinci_mdio-0:01"
|
||||
/*
|
||||
* A MAX-II CPLD is used for various board control functions.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
#include <mach/usb.h>
|
||||
#include <mach/aemif.h>
|
||||
|
||||
#define DM644X_EVM_PHY_ID "0:01"
|
||||
#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
|
||||
#define LXT971_PHY_ID (0x001378e2)
|
||||
#define LXT971_PHY_MASK (0xfffffff0)
|
||||
|
||||
|
|
|
|||
|
|
@ -736,7 +736,7 @@ static struct davinci_uart_config uart_config __initdata = {
|
|||
.enabled_uarts = (1 << 0),
|
||||
};
|
||||
|
||||
#define DM646X_EVM_PHY_ID "0:01"
|
||||
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
|
||||
/*
|
||||
* The following EDMA channels/slots are not being used by drivers (for
|
||||
* example: Timer, GPIO, UART events etc) on dm646x, hence they are being
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
#include <mach/mmc.h>
|
||||
#include <mach/usb.h>
|
||||
|
||||
#define NEUROS_OSD2_PHY_ID "0:01"
|
||||
#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
|
||||
#define LXT971_PHY_ID 0x001378e2
|
||||
#define LXT971_PHY_MASK 0xfffffff0
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include <mach/da8xx.h>
|
||||
#include <mach/mux.h>
|
||||
|
||||
#define HAWKBOARD_PHY_ID "0:07"
|
||||
#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
|
||||
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
|
||||
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
#include <mach/mux.h>
|
||||
#include <mach/usb.h>
|
||||
|
||||
#define SFFSDR_PHY_ID "0:01"
|
||||
#define SFFSDR_PHY_ID "davinci_mdio-0:01"
|
||||
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
|
||||
/* U-Boot Environment: Block 0
|
||||
* UBL: Block 1
|
||||
|
|
|
|||
|
|
@ -153,34 +153,6 @@ static struct clk pll1_sysclk3 = {
|
|||
.div_reg = PLLDIV3,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk4 = {
|
||||
.name = "pll1_sysclk4",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV4,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk5 = {
|
||||
.name = "pll1_sysclk5",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV5,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk6 = {
|
||||
.name = "pll0_sysclk6",
|
||||
.parent = &pll0_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV6,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk7 = {
|
||||
.name = "pll1_sysclk7",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV7,
|
||||
};
|
||||
|
||||
static struct clk i2c0_clk = {
|
||||
.name = "i2c0",
|
||||
.parent = &pll0_aux_clk,
|
||||
|
|
@ -397,10 +369,6 @@ static struct clk_lookup da850_clks[] = {
|
|||
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
||||
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
|
||||
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
|
||||
CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
|
||||
CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
|
||||
CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
|
||||
CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
|
||||
CLK("i2c_davinci.1", NULL, &i2c0_clk),
|
||||
CLK(NULL, "timer0", &timerp64_0_clk),
|
||||
CLK("watchdog", NULL, &timerp64_1_clk),
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <linux/irq.h>
|
||||
#include <plat/time.h>
|
||||
#include <plat/ehci-orion.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/addr-map.h>
|
||||
#include "common.h"
|
||||
|
|
@ -71,7 +72,7 @@ void __init dove_map_io(void)
|
|||
****************************************************************************/
|
||||
void __init dove_ehci0_init(void)
|
||||
{
|
||||
orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
|
||||
orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/fb.h>
|
||||
#include <mach/ep93xx_spi.h>
|
||||
#include <mach/gpio-ep93xx.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
|
|||
}, {
|
||||
I2C_BOARD_INFO("pca9539", 0x74),
|
||||
.platform_data = &pca953x_74_gpio_data,
|
||||
.irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
|
||||
}, {
|
||||
I2C_BOARD_INFO("pca9539", 0x75),
|
||||
.platform_data = &pca953x_75_gpio_data,
|
||||
|
|
@ -348,6 +348,8 @@ static void __init vision_init_machine(void)
|
|||
"pca9539:74"))
|
||||
pr_warn("cannot request interrupt gpio for pca9539:74\n");
|
||||
|
||||
vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
|
||||
|
||||
ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
|
||||
ARRAY_SIZE(vision_i2c_info));
|
||||
ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
#include "common.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
|
|
@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = {
|
|||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
|
|
|
|||
|
|
@ -32,12 +32,14 @@
|
|||
|
||||
#include "common.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include "common.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
|
||||
|
|
@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = {
|
|||
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
|
||||
};
|
||||
#endif
|
||||
|
||||
struct clk clk_sclk_hdmi27m = {
|
||||
.name = "sclk_hdmi27m",
|
||||
|
|
|
|||
|
|
@ -15,11 +15,13 @@
|
|||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/exynos4.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
|
|
@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
|
|||
|
||||
static void __init exynos4210_dt_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
|
|
@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
|||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = exynos4210_dt_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = exynos4210_dt_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
.dt_compat = exynos4210_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
|
|||
.lower_margin = 1,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1280,
|
||||
.yres = 800,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.refresh = 60,
|
||||
},
|
||||
.max_bpp = 24,
|
||||
.default_bpp = 16,
|
||||
.virtual_x = 1280,
|
||||
.virtual_y = 800,
|
||||
.virtual_x = 1024,
|
||||
.virtual_y = 2 * 600,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
|
||||
|
|
|
|||
|
|
@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
|
|||
.bus_type = FIMC_MIPI_CSI2,
|
||||
.board_info = &m5mols_board_info,
|
||||
.i2c_bus_num = 0,
|
||||
.clk_frequency = 21600000UL,
|
||||
.clk_frequency = 24000000UL,
|
||||
.csi_data_align = 32,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void)
|
|||
|
||||
}
|
||||
|
||||
static int exynos4_pm_add(struct device *dev)
|
||||
static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
pm_cpu_prep = exynos4_pm_prepare;
|
||||
pm_cpu_sleep = exynos4_cpu_suspend;
|
||||
|
|
@ -384,7 +384,9 @@ static void exynos4_pm_resume(void)
|
|||
|
||||
exynos4_restore_pll();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
scu_enable(S5P_VA_SCU);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <plat/cache-feroceon-l2.h>
|
||||
#include <plat/mvsdio.h>
|
||||
#include <plat/orion_nand.h>
|
||||
#include <plat/ehci-orion.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/time.h>
|
||||
#include <plat/addr-map.h>
|
||||
|
|
@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
|
|||
void __init kirkwood_ehci_init(void)
|
||||
{
|
||||
kirkwood_clk_ctrl |= CGC_USB0;
|
||||
orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
|
||||
orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -31,314 +31,314 @@
|
|||
#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 )
|
||||
|
||||
#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 )
|
||||
|
||||
#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 )
|
||||
|
||||
#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 )
|
||||
#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
|
||||
#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
|
||||
#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
|
||||
#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 )
|
||||
#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
|
||||
#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 )
|
||||
#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
|
||||
#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 )
|
||||
|
||||
#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
|
||||
#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 )
|
||||
#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
|
||||
#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
|
||||
#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
|
||||
#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
|
||||
#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
|
||||
#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 )
|
||||
#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 )
|
||||
#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 )
|
||||
#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 )
|
||||
#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
|
||||
|
||||
#define MPP_MAX 49
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <mach/mv78xx0.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/cache-feroceon-l2.h>
|
||||
#include <plat/ehci-orion.h>
|
||||
#include <plat/orion_nand.h>
|
||||
#include <plat/time.h>
|
||||
#include <plat/common.h>
|
||||
|
|
@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void)
|
|||
****************************************************************************/
|
||||
void __init mv78xx0_ehci0_init(void)
|
||||
{
|
||||
orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
|
||||
orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -24,296 +24,296 @@
|
|||
#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
|
||||
|
||||
#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
|
||||
#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1)
|
||||
#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1)
|
||||
#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
|
||||
#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
|
||||
#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
|
||||
#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1)
|
||||
#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1)
|
||||
#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
|
||||
#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
|
||||
#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
|
||||
#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1)
|
||||
#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1)
|
||||
#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
|
||||
#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
|
||||
#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
|
||||
#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1)
|
||||
#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1)
|
||||
#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
|
||||
#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
|
||||
#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
|
||||
#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1)
|
||||
#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1)
|
||||
#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
|
||||
#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
|
||||
#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
|
||||
#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1)
|
||||
#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1)
|
||||
#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
|
||||
#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
|
||||
#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
|
||||
#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1)
|
||||
#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1)
|
||||
#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
|
||||
#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
|
||||
#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
|
||||
#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1)
|
||||
#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1)
|
||||
#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
|
||||
#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
|
||||
#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
|
||||
#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1)
|
||||
#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1)
|
||||
#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
|
||||
#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
|
||||
#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
|
||||
#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1)
|
||||
#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1)
|
||||
#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
|
||||
#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
|
||||
#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
|
||||
#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1)
|
||||
#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1)
|
||||
#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
|
||||
#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
|
||||
#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
|
||||
#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1)
|
||||
#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1)
|
||||
#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
|
||||
#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
|
||||
#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
|
||||
#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1)
|
||||
#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1)
|
||||
#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1)
|
||||
#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1)
|
||||
#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
|
||||
#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
|
||||
#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
|
||||
#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
|
||||
#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
|
||||
#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1)
|
||||
#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1)
|
||||
#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1)
|
||||
#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1)
|
||||
#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
|
||||
#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
|
||||
#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
|
||||
#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
|
||||
#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
|
||||
#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1)
|
||||
#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1)
|
||||
#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1)
|
||||
#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1)
|
||||
#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
|
||||
#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
|
||||
#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
|
||||
#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
|
||||
#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
|
||||
#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1)
|
||||
#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1)
|
||||
#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1)
|
||||
#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1)
|
||||
#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
|
||||
#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
|
||||
#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
|
||||
#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
|
||||
#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
|
||||
#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1)
|
||||
#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1)
|
||||
#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1)
|
||||
#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1)
|
||||
#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
|
||||
#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
|
||||
#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
|
||||
#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
|
||||
#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
|
||||
#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1)
|
||||
#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1)
|
||||
#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1)
|
||||
#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1)
|
||||
#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
|
||||
#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
|
||||
#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
|
||||
#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
|
||||
#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
|
||||
#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1)
|
||||
#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1)
|
||||
#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
|
||||
#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
|
||||
#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
|
||||
#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1)
|
||||
#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1)
|
||||
#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
|
||||
#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
|
||||
#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
|
||||
#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1)
|
||||
#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0)
|
||||
#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
|
||||
#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
|
||||
#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
|
||||
#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1)
|
||||
#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0)
|
||||
#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
|
||||
#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
|
||||
#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
|
||||
#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1)
|
||||
#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1)
|
||||
#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1)
|
||||
#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
|
||||
#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
|
||||
#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
|
||||
#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
|
||||
#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1)
|
||||
#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1)
|
||||
#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1)
|
||||
#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
|
||||
#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
|
||||
#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
|
||||
#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
|
||||
#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1)
|
||||
#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1)
|
||||
#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
|
||||
#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
|
||||
#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
|
||||
#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1)
|
||||
#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1)
|
||||
#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
|
||||
#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
|
||||
#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
|
||||
#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1)
|
||||
#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1)
|
||||
#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
|
||||
#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
|
||||
#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
|
||||
#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1)
|
||||
#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1)
|
||||
#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
|
||||
#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
|
||||
#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
|
||||
#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1)
|
||||
#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1)
|
||||
#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
|
||||
#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
|
||||
#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
|
||||
#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1)
|
||||
#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1)
|
||||
#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1)
|
||||
#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
|
||||
#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
|
||||
#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
|
||||
#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
|
||||
#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1)
|
||||
#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
|
||||
#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
|
||||
|
||||
#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
|
||||
#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1)
|
||||
#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1)
|
||||
#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
|
||||
#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
|
||||
#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
|
||||
#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1)
|
||||
#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1)
|
||||
#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1)
|
||||
#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
|
||||
#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
|
||||
#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
|
||||
#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
|
||||
#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1)
|
||||
#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1)
|
||||
#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
|
||||
#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
|
||||
#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
|
||||
#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1)
|
||||
#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1)
|
||||
#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
|
||||
#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
|
||||
#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
|
||||
#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1)
|
||||
#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1)
|
||||
#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
|
||||
#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
|
||||
#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
|
||||
|
||||
#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
|
||||
#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1)
|
||||
#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1)
|
||||
#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1)
|
||||
#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
|
||||
#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
|
||||
#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
|
||||
#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
|
||||
#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1)
|
||||
#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1)
|
||||
#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1)
|
||||
#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1)
|
||||
#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
|
||||
#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
|
||||
#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
|
||||
#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
|
||||
#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
|
||||
#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
|
||||
#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1)
|
||||
#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1)
|
||||
#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1)
|
||||
#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1)
|
||||
#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
|
||||
#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
|
||||
#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
|
||||
#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
|
||||
#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
|
||||
#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
|
||||
#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1)
|
||||
#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1)
|
||||
#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1)
|
||||
#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1)
|
||||
#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
|
||||
#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
|
||||
#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
|
||||
#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
|
||||
#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
|
||||
#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1)
|
||||
#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
|
||||
#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
|
||||
#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1)
|
||||
#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
|
||||
#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
|
||||
#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1)
|
||||
#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
|
||||
#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
|
||||
#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1)
|
||||
#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
|
||||
#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
|
||||
#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1)
|
||||
#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
|
||||
#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
|
||||
#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1)
|
||||
#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1)
|
||||
#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
|
||||
#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
|
||||
#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
|
||||
#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1)
|
||||
#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
|
||||
#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
|
||||
|
||||
|
||||
|
|
@ -323,14 +323,14 @@
|
|||
|
||||
|
||||
#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
|
||||
#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1)
|
||||
#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
|
||||
#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
|
||||
|
||||
|
||||
|
||||
#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
|
||||
#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1)
|
||||
#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1)
|
||||
#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
|
||||
#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
|
||||
#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -213,13 +213,12 @@ config MACH_OMAP3_PANDORA
|
|||
depends on ARCH_OMAP3
|
||||
default y
|
||||
select OMAP_PACKAGE_CBB
|
||||
select REGULATOR_FIXED_VOLTAGE
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_OMAP3_TOUCHBOOK
|
||||
bool "OMAP3 Touch Book"
|
||||
depends on ARCH_OMAP3
|
||||
default y
|
||||
select BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
config MACH_OMAP_3430SDP
|
||||
bool "OMAP 3430 SDP board"
|
||||
|
|
@ -265,7 +264,7 @@ config MACH_OMAP_ZOOM2
|
|||
select SERIAL_8250
|
||||
select SERIAL_CORE_CONSOLE
|
||||
select SERIAL_8250_CONSOLE
|
||||
select REGULATOR_FIXED_VOLTAGE
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_OMAP_ZOOM3
|
||||
bool "OMAP3630 Zoom3 board"
|
||||
|
|
@ -275,7 +274,7 @@ config MACH_OMAP_ZOOM3
|
|||
select SERIAL_8250
|
||||
select SERIAL_CORE_CONSOLE
|
||||
select SERIAL_8250_CONSOLE
|
||||
select REGULATOR_FIXED_VOLTAGE
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_CM_T35
|
||||
bool "CompuLab CM-T35/CM-T3730 modules"
|
||||
|
|
@ -334,7 +333,7 @@ config MACH_OMAP_4430SDP
|
|||
depends on ARCH_OMAP4
|
||||
select OMAP_PACKAGE_CBL
|
||||
select OMAP_PACKAGE_CBS
|
||||
select REGULATOR_FIXED_VOLTAGE
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_OMAP4_PANDA
|
||||
bool "OMAP4 Panda Board"
|
||||
|
|
@ -342,7 +341,7 @@ config MACH_OMAP4_PANDA
|
|||
depends on ARCH_OMAP4
|
||||
select OMAP_PACKAGE_CBL
|
||||
select OMAP_PACKAGE_CBS
|
||||
select REGULATOR_FIXED_VOLTAGE
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config OMAP3_EMU
|
||||
bool "OMAP3 debugging peripherals"
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \
|
|||
omap_hwmod_common_data.o
|
||||
clock-common = clock.o clock_common_data.o \
|
||||
clkt_dpll.o clkt_clksel.o
|
||||
secure-common = omap-smc.o omap-secure.o
|
||||
secure-common = omap-smc.o omap-secure.o
|
||||
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,8 +52,9 @@
|
|||
#define ETH_KS8851_QUART 138
|
||||
#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
|
||||
#define OMAP4_SFH7741_ENABLE_GPIO 188
|
||||
#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
|
||||
#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
|
||||
#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
|
||||
#define HDMI_GPIO_HPD 63 /* Hotplug detect */
|
||||
#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */
|
||||
#define DLP_POWER_ON_GPIO 40
|
||||
|
||||
|
|
@ -603,8 +604,9 @@ static void __init omap_sfh7741prox_init(void)
|
|||
}
|
||||
|
||||
static struct gpio sdp4430_hdmi_gpios[] = {
|
||||
{ HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
|
||||
{ HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
|
||||
{ HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
|
||||
{ HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
|
||||
};
|
||||
|
||||
static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
|
||||
|
|
@ -621,8 +623,7 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
|
|||
|
||||
static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
|
||||
{
|
||||
gpio_free(HDMI_GPIO_LS_OE);
|
||||
gpio_free(HDMI_GPIO_HPD);
|
||||
gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios));
|
||||
}
|
||||
|
||||
static struct nokia_dsi_panel_data dsi1_panel = {
|
||||
|
|
@ -738,6 +739,10 @@ static void sdp4430_lcd_init(void)
|
|||
pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
|
||||
}
|
||||
|
||||
static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
|
||||
.hpd_gpio = HDMI_GPIO_HPD,
|
||||
};
|
||||
|
||||
static struct omap_dss_device sdp4430_hdmi_device = {
|
||||
.name = "hdmi",
|
||||
.driver_name = "hdmi_panel",
|
||||
|
|
@ -745,6 +750,7 @@ static struct omap_dss_device sdp4430_hdmi_device = {
|
|||
.platform_enable = sdp4430_panel_enable_hdmi,
|
||||
.platform_disable = sdp4430_panel_disable_hdmi,
|
||||
.channel = OMAP_DSS_CHANNEL_DIGIT,
|
||||
.data = &sdp4430_hdmi_data,
|
||||
};
|
||||
|
||||
static struct picodlp_panel_data sdp4430_picodlp_pdata = {
|
||||
|
|
@ -808,7 +814,7 @@ static struct omap_dss_board_info sdp4430_dss_data = {
|
|||
.default_device = &sdp4430_lcd_device,
|
||||
};
|
||||
|
||||
static void omap_4430sdp_display_init(void)
|
||||
static void __init omap_4430sdp_display_init(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
|
|
@ -829,6 +835,10 @@ static void omap_4430sdp_display_init(void)
|
|||
omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
|
||||
else
|
||||
omap_hdmi_init(0);
|
||||
|
||||
omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -841,7 +851,7 @@ static struct omap_board_mux board_mux[] __initdata = {
|
|||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void omap4_sdp4430_wifi_mux_init(void)
|
||||
static void __init omap4_sdp4430_wifi_mux_init(void)
|
||||
{
|
||||
omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
|
||||
OMAP_PIN_OFF_WAKEUPENABLE);
|
||||
|
|
@ -868,12 +878,17 @@ static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
|
|||
.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
|
||||
};
|
||||
|
||||
static void omap4_sdp4430_wifi_init(void)
|
||||
static void __init omap4_sdp4430_wifi_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
omap4_sdp4430_wifi_mux_init();
|
||||
if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data))
|
||||
pr_err("Error setting wl12xx data\n");
|
||||
platform_device_register(&omap_vwlan_device);
|
||||
ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
|
||||
if (ret)
|
||||
pr_err("Error setting wl12xx data: %d\n", ret);
|
||||
ret = platform_device_register(&omap_vwlan_device);
|
||||
if (ret)
|
||||
pr_err("Error registering wl12xx device: %d\n", ret);
|
||||
}
|
||||
|
||||
static void __init omap_4430sdp_init(void)
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static void cm_t35_init_usbh(void)
|
||||
static void __init cm_t35_init_usbh(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/i2c/twl.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include <plat/board.h>
|
||||
|
|
@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
|
|||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.handle_irq = omap2_intc_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.timer = &omap2_timer,
|
||||
.dt_compat = omap242x_boards_compat,
|
||||
|
|
@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
|
|||
.map_io = omap3_map_io,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = omap3_init,
|
||||
.timer = &omap3_timer,
|
||||
.dt_compat = omap3_boards_compat,
|
||||
|
|
@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
|
|||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = omap4_init,
|
||||
.timer = &omap4_timer,
|
||||
.dt_compat = omap4_boards_compat,
|
||||
|
|
|
|||
|
|
@ -617,6 +617,21 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = {
|
|||
{ OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
|
||||
};
|
||||
|
||||
static void __init omap3_evm_wl12xx_init(void)
|
||||
{
|
||||
#ifdef CONFIG_WL12XX_PLATFORM_DATA
|
||||
int ret;
|
||||
|
||||
/* WL12xx WLAN Init */
|
||||
ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
|
||||
if (ret)
|
||||
pr_err("error setting wl12xx data: %d\n", ret);
|
||||
ret = platform_device_register(&omap3evm_wlan_regulator);
|
||||
if (ret)
|
||||
pr_err("error registering wl12xx device: %d\n", ret);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init omap3_evm_init(void)
|
||||
{
|
||||
omap3_evm_get_revision();
|
||||
|
|
@ -665,13 +680,7 @@ static void __init omap3_evm_init(void)
|
|||
omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
|
||||
omap3evm_init_smsc911x();
|
||||
omap3_evm_display_init();
|
||||
|
||||
#ifdef CONFIG_WL12XX_PLATFORM_DATA
|
||||
/* WL12xx WLAN Init */
|
||||
if (wl12xx_set_platform_data(&omap3evm_wlan_data))
|
||||
pr_err("error setting wl12xx data\n");
|
||||
platform_device_register(&omap3evm_wlan_regulator);
|
||||
#endif
|
||||
omap3_evm_wl12xx_init();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP3EVM, "OMAP3 EVM")
|
||||
|
|
|
|||
|
|
@ -51,8 +51,9 @@
|
|||
#define GPIO_HUB_NRESET 62
|
||||
#define GPIO_WIFI_PMENA 43
|
||||
#define GPIO_WIFI_IRQ 53
|
||||
#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
|
||||
#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
|
||||
#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
|
||||
#define HDMI_GPIO_HPD 63 /* Hotplug detect */
|
||||
|
||||
/* wl127x BT, FM, GPS connectivity chip */
|
||||
static int wl1271_gpios[] = {46, -1, -1};
|
||||
|
|
@ -413,8 +414,9 @@ int __init omap4_panda_dvi_init(void)
|
|||
}
|
||||
|
||||
static struct gpio panda_hdmi_gpios[] = {
|
||||
{ HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
|
||||
{ HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
|
||||
{ HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
|
||||
{ HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
|
||||
};
|
||||
|
||||
static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
|
||||
|
|
@ -431,10 +433,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
|
|||
|
||||
static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
|
||||
{
|
||||
gpio_free(HDMI_GPIO_LS_OE);
|
||||
gpio_free(HDMI_GPIO_HPD);
|
||||
gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios));
|
||||
}
|
||||
|
||||
static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
|
||||
.hpd_gpio = HDMI_GPIO_HPD,
|
||||
};
|
||||
|
||||
static struct omap_dss_device omap4_panda_hdmi_device = {
|
||||
.name = "hdmi",
|
||||
.driver_name = "hdmi_panel",
|
||||
|
|
@ -442,6 +447,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = {
|
|||
.platform_enable = omap4_panda_panel_enable_hdmi,
|
||||
.platform_disable = omap4_panda_panel_disable_hdmi,
|
||||
.channel = OMAP_DSS_CHANNEL_DIGIT,
|
||||
.data = &omap4_panda_hdmi_data,
|
||||
};
|
||||
|
||||
static struct omap_dss_device *omap4_panda_dss_devices[] = {
|
||||
|
|
@ -473,18 +479,24 @@ void omap4_panda_display_init(void)
|
|||
omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
|
||||
else
|
||||
omap_hdmi_init(0);
|
||||
|
||||
omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
|
||||
}
|
||||
|
||||
static void __init omap4_panda_init(void)
|
||||
{
|
||||
int package = OMAP_PACKAGE_CBS;
|
||||
int ret;
|
||||
|
||||
if (omap_rev() == OMAP4430_REV_ES1_0)
|
||||
package = OMAP_PACKAGE_CBL;
|
||||
omap4_mux_init(board_mux, NULL, package);
|
||||
|
||||
if (wl12xx_set_platform_data(&omap_panda_wlan_data))
|
||||
pr_err("error setting wl12xx data\n");
|
||||
ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
|
||||
if (ret)
|
||||
pr_err("error setting wl12xx data: %d\n", ret);
|
||||
|
||||
omap4_panda_i2c_init();
|
||||
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
|
||||
|
|
|
|||
|
|
@ -296,8 +296,10 @@ static void enable_board_wakeup_source(void)
|
|||
|
||||
void __init zoom_peripherals_init(void)
|
||||
{
|
||||
if (wl12xx_set_platform_data(&omap_zoom_wlan_data))
|
||||
pr_err("error setting wl12xx data\n");
|
||||
int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
|
||||
|
||||
if (ret)
|
||||
pr_err("error setting wl12xx data: %d\n", ret);
|
||||
|
||||
omap_i2c_init();
|
||||
platform_device_register(&omap_vwlan_device);
|
||||
|
|
|
|||
|
|
@ -405,6 +405,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
|
|||
break;
|
||||
default:
|
||||
pr_err("Invalid McSPI Revision value\n");
|
||||
kfree(pdata);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -103,12 +103,8 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
|
|||
u32 reg;
|
||||
u16 control_i2c_1;
|
||||
|
||||
/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
|
||||
omap_mux_init_signal("hdmi_hpd",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("hdmi_cec",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
|
||||
omap_mux_init_signal("hdmi_ddc_scl",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("hdmi_ddc_sda",
|
||||
|
|
|
|||
|
|
@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
|
|||
|
||||
case GPMC_CONFIG_DEV_SIZE:
|
||||
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
|
||||
/* clear 2 target bits */
|
||||
regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
|
||||
|
||||
/* set the proper value */
|
||||
regval |= GPMC_CONFIG1_DEVICESIZE(wval);
|
||||
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -175,14 +175,15 @@ static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
|
|||
{
|
||||
u32 reg;
|
||||
|
||||
if (mmc->slots[0].internal_clock) {
|
||||
reg = omap_ctrl_readl(control_devconf1_offset);
|
||||
reg = omap_ctrl_readl(control_devconf1_offset);
|
||||
if (mmc->slots[0].internal_clock)
|
||||
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
|
||||
omap_ctrl_writel(reg, control_devconf1_offset);
|
||||
}
|
||||
else
|
||||
reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
|
||||
omap_ctrl_writel(reg, control_devconf1_offset);
|
||||
}
|
||||
|
||||
static void hsmmc23_before_set_reg(struct device *dev, int slot,
|
||||
static void hsmmc2_before_set_reg(struct device *dev, int slot,
|
||||
int power_on, int vdd)
|
||||
{
|
||||
struct omap_mmc_platform_data *mmc = dev->platform_data;
|
||||
|
|
@ -292,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
|
|||
}
|
||||
}
|
||||
|
||||
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
struct omap_mmc_platform_data *mmc)
|
||||
static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
struct omap_mmc_platform_data *mmc)
|
||||
{
|
||||
char *hc_name;
|
||||
|
||||
|
|
@ -407,14 +408,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
|||
c->caps &= ~MMC_CAP_8_BIT_DATA;
|
||||
c->caps |= MMC_CAP_4_BIT_DATA;
|
||||
}
|
||||
/* FALLTHROUGH */
|
||||
case 3:
|
||||
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
|
||||
/* off-chip level shifting, or none */
|
||||
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
|
||||
mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
|
||||
mmc->slots[0].after_set_reg = NULL;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
case 4:
|
||||
case 5:
|
||||
mmc->slots[0].before_set_reg = NULL;
|
||||
|
|
@ -430,7 +430,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
|||
|
||||
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
|
||||
|
||||
void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
{
|
||||
struct omap_hwmod *oh;
|
||||
struct platform_device *pdev;
|
||||
|
|
@ -487,7 +487,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
|||
kfree(mmc_data);
|
||||
}
|
||||
|
||||
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
||||
void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
|
|||
|
|
@ -388,7 +388,7 @@ static void __init omap_hwmod_init_postsetup(void)
|
|||
omap_pm_if_early_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
void __init omap2420_init_early(void)
|
||||
{
|
||||
omap2_set_globals_242x();
|
||||
|
|
@ -400,7 +400,9 @@ void __init omap2420_init_early(void)
|
|||
omap_hwmod_init_postsetup();
|
||||
omap2420_clk_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
void __init omap2430_init_early(void)
|
||||
{
|
||||
omap2_set_globals_243x();
|
||||
|
|
|
|||
|
|
@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
|
|||
|
||||
static char *omap_mux_options;
|
||||
|
||||
static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
|
||||
int gpio, int val)
|
||||
static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
|
||||
int gpio, int val)
|
||||
{
|
||||
struct omap_mux_entry *e;
|
||||
struct omap_mux *gpio_mux = NULL;
|
||||
|
|
@ -145,7 +145,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int __init omap_mux_init_gpio(int gpio, int val)
|
||||
int omap_mux_init_gpio(int gpio, int val)
|
||||
{
|
||||
struct omap_mux_partition *partition;
|
||||
int ret;
|
||||
|
|
@ -159,9 +159,9 @@ int __init omap_mux_init_gpio(int gpio, int val)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
|
||||
const char *muxname,
|
||||
struct omap_mux **found_mux)
|
||||
static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
|
||||
const char *muxname,
|
||||
struct omap_mux **found_mux)
|
||||
{
|
||||
struct omap_mux *mux = NULL;
|
||||
struct omap_mux_entry *e;
|
||||
|
|
@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
int __init omap_mux_init_signal(const char *muxname, int val)
|
||||
int omap_mux_init_signal(const char *muxname, int val)
|
||||
{
|
||||
struct omap_mux_partition *partition = NULL;
|
||||
struct omap_mux *mux = NULL;
|
||||
|
|
@ -1094,8 +1094,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
|
|||
omap_mux_package_init_balls(package_balls, superset);
|
||||
}
|
||||
|
||||
static void omap_mux_init_signals(struct omap_mux_partition *partition,
|
||||
struct omap_board_mux *board_mux)
|
||||
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
|
||||
struct omap_board_mux *board_mux)
|
||||
{
|
||||
omap_mux_set_cmdline_signals();
|
||||
omap_mux_write_array(partition, board_mux);
|
||||
|
|
@ -1109,8 +1109,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
|
|||
{
|
||||
}
|
||||
|
||||
static void omap_mux_init_signals(struct omap_mux_partition *partition,
|
||||
struct omap_board_mux *board_mux)
|
||||
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
|
||||
struct omap_board_mux *board_mux)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
__CPUINIT
|
||||
/*
|
||||
* OMAP4 specific entry point for secondary CPU to jump from ROM
|
||||
* code. This routine also provides a holding flag into which
|
||||
|
|
|
|||
|
|
@ -1517,8 +1517,8 @@ static int _enable(struct omap_hwmod *oh)
|
|||
if (oh->_state != _HWMOD_STATE_INITIALIZED &&
|
||||
oh->_state != _HWMOD_STATE_IDLE &&
|
||||
oh->_state != _HWMOD_STATE_DISABLED) {
|
||||
WARN(1, "omap_hwmod: %s: enabled state can only be entered "
|
||||
"from initialized, idle, or disabled state\n", oh->name);
|
||||
WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
|
||||
oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -1600,8 +1600,8 @@ static int _idle(struct omap_hwmod *oh)
|
|||
pr_debug("omap_hwmod: %s: idling\n", oh->name);
|
||||
|
||||
if (oh->_state != _HWMOD_STATE_ENABLED) {
|
||||
WARN(1, "omap_hwmod: %s: idle state can only be entered from "
|
||||
"enabled state\n", oh->name);
|
||||
WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
|
||||
oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -1682,8 +1682,8 @@ static int _shutdown(struct omap_hwmod *oh)
|
|||
|
||||
if (oh->_state != _HWMOD_STATE_IDLE &&
|
||||
oh->_state != _HWMOD_STATE_ENABLED) {
|
||||
WARN(1, "omap_hwmod: %s: disabled state can only be entered "
|
||||
"from idle, or enabled state\n", oh->name);
|
||||
WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
|
||||
oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -2240,8 +2240,8 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
|
|||
BUG_ON(!oh);
|
||||
|
||||
if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
|
||||
WARN(1, "omap_device: %s: OCP barrier impossible due to "
|
||||
"device configuration\n", oh->name);
|
||||
WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
|
||||
oh->name);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -55,27 +55,6 @@ struct omap_hwmod_class omap2_dss_hwmod_class = {
|
|||
.reset = omap_dss_reset,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dispc' class
|
||||
* display controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_dispc_hwmod_class = {
|
||||
.name = "dispc",
|
||||
.sysc = &omap2_dispc_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'rfbi' class
|
||||
* remote frame buffer interface
|
||||
|
|
|
|||
|
|
@ -28,6 +28,28 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
|
|||
{ .name = "dispc", .dma_req = 5 },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dispc' class
|
||||
* display controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_dispc_hwmod_class = {
|
||||
.name = "dispc",
|
||||
.sysc = &omap2_dispc_sysc,
|
||||
};
|
||||
|
||||
/* OMAP2xxx Timer Common */
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
|
|
|
|||
|
|
@ -1480,6 +1480,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
|
|||
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dispc' class
|
||||
* display controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
||||
SYSC_HAS_ENAWAKEUP),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap3_dispc_hwmod_class = {
|
||||
.name = "dispc",
|
||||
.sysc = &omap3_dispc_sysc,
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
|
|
@ -1503,7 +1525,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap2_dispc_hwmod_class,
|
||||
.class = &omap3_dispc_hwmod_class,
|
||||
.mpu_irqs = omap2_dispc_irqs,
|
||||
.main_clk = "dss1_alwon_fck",
|
||||
.prcm = {
|
||||
|
|
@ -3523,12 +3545,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
|||
&omap3xxx_uart2_hwmod,
|
||||
&omap3xxx_uart3_hwmod,
|
||||
|
||||
/* dss class */
|
||||
&omap3xxx_dss_dispc_hwmod,
|
||||
&omap3xxx_dss_dsi1_hwmod,
|
||||
&omap3xxx_dss_rfbi_hwmod,
|
||||
&omap3xxx_dss_venc_hwmod,
|
||||
|
||||
/* i2c class */
|
||||
&omap3xxx_i2c1_hwmod,
|
||||
&omap3xxx_i2c2_hwmod,
|
||||
|
|
@ -3635,6 +3651,15 @@ static __initdata struct omap_hwmod *am35xx_hwmods[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
|
||||
/* dss class */
|
||||
&omap3xxx_dss_dispc_hwmod,
|
||||
&omap3xxx_dss_dsi1_hwmod,
|
||||
&omap3xxx_dss_rfbi_hwmod,
|
||||
&omap3xxx_dss_venc_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
int __init omap3xxx_hwmod_init(void)
|
||||
{
|
||||
int r;
|
||||
|
|
@ -3708,6 +3733,21 @@ int __init omap3xxx_hwmod_init(void)
|
|||
|
||||
if (h)
|
||||
r = omap_hwmod_register(h);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
/*
|
||||
* DSS code presumes that dss_core hwmod is handled first,
|
||||
* _before_ any other DSS related hwmods so register common
|
||||
* DSS hwmods last to ensure that dss_core is already registered.
|
||||
* Otherwise some change things may happen, for ex. if dispc
|
||||
* is handled before dss_core and DSS is enabled in bootloader
|
||||
* DIPSC will be reset with outputs enabled which sometimes leads
|
||||
* to unrecoverable L3 error.
|
||||
* XXX The long-term fix to this is to ensure modules are set up
|
||||
* in dependency order in the hwmod core code.
|
||||
*/
|
||||
r = omap_hwmod_register(omap3xxx_dss_hwmods);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1031,6 +1031,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
|
|||
|
||||
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x4012e000,
|
||||
.pa_end = 0x4012e07f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
|
|
@ -1049,6 +1050,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
|
|||
|
||||
static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
|
||||
{
|
||||
.name = "dma",
|
||||
.pa_start = 0x4902e000,
|
||||
.pa_end = 0x4902e07f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
|
|
|
|||
|
|
@ -82,13 +82,7 @@ static int omap2_fclks_active(void)
|
|||
f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
|
||||
f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
|
||||
|
||||
/* Ignore UART clocks. These are handled by UART core (serial.c) */
|
||||
f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
|
||||
f2 &= ~OMAP24XX_EN_UART3_MASK;
|
||||
|
||||
if (f1 | f2)
|
||||
return 1;
|
||||
return 0;
|
||||
return (f1 | f2) ? 1 : 0;
|
||||
}
|
||||
|
||||
static void omap2_enter_full_retention(void)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include "common.h"
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/prcm.h>
|
||||
#include <plat/irqs.h>
|
||||
|
||||
#include "vp.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "common.h"
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/prcm.h>
|
||||
|
||||
#include "vp.h"
|
||||
|
|
|
|||
|
|
@ -107,18 +107,18 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
|
|||
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
|
||||
}
|
||||
|
||||
static void omap_uart_set_forceidle(struct platform_device *pdev)
|
||||
static void omap_uart_set_smartidle(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_device *od = to_omap_device(pdev);
|
||||
|
||||
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
|
||||
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
|
||||
}
|
||||
|
||||
#else
|
||||
static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
|
||||
{}
|
||||
static void omap_uart_set_noidle(struct platform_device *pdev) {}
|
||||
static void omap_uart_set_forceidle(struct platform_device *pdev) {}
|
||||
static void omap_uart_set_smartidle(struct platform_device *pdev) {}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -349,7 +349,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
|
|||
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
|
||||
omap_up.flags = UPF_BOOT_AUTOCONF;
|
||||
omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
|
||||
omap_up.set_forceidle = omap_uart_set_forceidle;
|
||||
omap_up.set_forceidle = omap_uart_set_smartidle;
|
||||
omap_up.set_noidle = omap_uart_set_noidle;
|
||||
omap_up.enable_wakeup = omap_uart_enable_wakeup;
|
||||
omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
|
||||
|
|
|
|||
|
|
@ -897,7 +897,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
|||
ret = sr_late_init(sr_info);
|
||||
if (ret) {
|
||||
pr_warning("%s: Error in SR late init\n", __func__);
|
||||
return ret;
|
||||
goto err_iounmap;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -270,7 +270,7 @@ static struct clocksource clocksource_gpt = {
|
|||
static u32 notrace dmtimer_read_sched_clock(void)
|
||||
{
|
||||
if (clksrc.reserved)
|
||||
return __omap_dm_timer_read_counter(clksrc.io_base, 1);
|
||||
return __omap_dm_timer_read_counter(&clksrc, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
|
|||
* omap_vc_i2c_init - initialize I2C interface to PMIC
|
||||
* @voltdm: voltage domain containing VC data
|
||||
*
|
||||
* Use PMIC supplied seetings for I2C high-speed mode and
|
||||
* Use PMIC supplied settings for I2C high-speed mode and
|
||||
* master code (if set) and program the VC I2C configuration
|
||||
* register.
|
||||
*
|
||||
|
|
@ -265,8 +265,8 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
|
|||
|
||||
if (initialized) {
|
||||
if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
|
||||
pr_warn("%s: I2C config for all channels must match.",
|
||||
__func__);
|
||||
pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
|
||||
__func__, voltdm->name, i2c_high_speed);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -292,9 +292,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
|
|||
u32 val;
|
||||
|
||||
if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
|
||||
pr_err("%s: PMIC info requried to configure vc for"
|
||||
"vdd_%s not populated.Hence cannot initialize vc\n",
|
||||
__func__, voltdm->name);
|
||||
pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void)
|
|||
* XXX Will depend on the process, validation, and binning
|
||||
* for the currently-running IC
|
||||
*/
|
||||
#ifdef CONFIG_PM_OPP
|
||||
if (cpu_is_omap3630()) {
|
||||
omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
|
||||
omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
|
||||
|
|
@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void)
|
|||
omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
|
||||
omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505())
|
||||
voltdms = voltagedomains_am35xx;
|
||||
|
|
|
|||
|
|
@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void)
|
|||
* XXX Will depend on the process, validation, and binning
|
||||
* for the currently-running IC
|
||||
*/
|
||||
#ifdef CONFIG_PM_OPP
|
||||
omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
|
||||
omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
|
||||
omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
|
||||
#endif
|
||||
|
||||
for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
|
||||
voltdm->sys_clk.name = sys_clk_name;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,11 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
|
|||
u32 val, sys_clk_rate, timeout, waittime;
|
||||
u32 vddmin, vddmax, vstepmin, vstepmax;
|
||||
|
||||
if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
|
||||
pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!voltdm->read || !voltdm->write) {
|
||||
pr_err("%s: No read/write API for accessing vdd_%s regs\n",
|
||||
__func__, voltdm->name);
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/orion5x.h>
|
||||
#include <plat/orion_nand.h>
|
||||
#include <plat/ehci-orion.h>
|
||||
#include <plat/time.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/addr-map.h>
|
||||
|
|
@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
|
|||
****************************************************************************/
|
||||
void __init orion5x_ehci0_init(void)
|
||||
{
|
||||
orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
|
||||
orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
|
||||
EHCI_PHY_ORION);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
|
|||
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
|
||||
};
|
||||
|
||||
static int s3c2410_cpufreq_add(struct device *dev)
|
||||
static int s3c2410_cpufreq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
return s3c_cpufreq_register(&s3c2410_cpufreq_info);
|
||||
}
|
||||
|
|
@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void)
|
|||
|
||||
arch_initcall(s3c2410_cpufreq_init);
|
||||
|
||||
static int s3c2410a_cpufreq_add(struct device *dev)
|
||||
static int s3c2410a_cpufreq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
/* alter the maximum freq settings for S3C2410A. If a board knows
|
||||
* it only has a maximum of 200, then it should register its own
|
||||
|
|
@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev)
|
|||
s3c2410_cpufreq_info.max.pclk = 66500000;
|
||||
s3c2410_cpufreq_info.name = "s3c2410a";
|
||||
|
||||
return s3c2410_cpufreq_add(dev);
|
||||
return s3c2410_cpufreq_add(dev, sif);
|
||||
}
|
||||
|
||||
static struct subsys_interface s3c2410a_cpufreq_interface = {
|
||||
|
|
|
|||
|
|
@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
|
|||
},
|
||||
};
|
||||
|
||||
static int __init s3c2410_dma_add(struct device *dev)
|
||||
static int __init s3c2410_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
s3c24xx_dma_order_set(&s3c2410_dma_order);
|
||||
|
|
@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = {
|
|||
|
||||
static int __init s3c2410_dma_drvinit(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2410_interface);
|
||||
return subsys_interface_register(&s3c2410_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_dma_drvinit);
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
|
|||
{ .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
|
||||
};
|
||||
|
||||
static int s3c2410_plls_add(struct device *dev)
|
||||
static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
|
|||
.resume = s3c2410_pm_resume,
|
||||
};
|
||||
|
||||
static int s3c2410_pm_add(struct device *dev)
|
||||
static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
pm_cpu_prep = s3c2410_pm_prepare;
|
||||
pm_cpu_sleep = s3c2410_cpu_suspend;
|
||||
|
|
|
|||
|
|
@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
|
|||
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
|
||||
};
|
||||
|
||||
static int s3c2412_cpufreq_add(struct device *dev)
|
||||
static int s3c2412_cpufreq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
unsigned long fclk_rate;
|
||||
|
||||
|
|
|
|||
|
|
@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
|
|||
.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
|
||||
};
|
||||
|
||||
static int __init s3c2412_dma_add(struct device *dev)
|
||||
static int __init s3c2412_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
return s3c24xx_dma_init_map(&s3c2412_dma_sel);
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
|
|||
|
||||
static struct irq_chip s3c2412_irq_rtc_chip;
|
||||
|
||||
static int s3c2412_irq_add(struct device *dev)
|
||||
static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
|
|||
{
|
||||
}
|
||||
|
||||
static int s3c2412_pm_add(struct device *dev)
|
||||
static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
pm_cpu_prep = s3c2412_pm_prepare;
|
||||
pm_cpu_sleep = s3c2412_cpu_suspend;
|
||||
|
|
|
|||
|
|
@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int __init s3c2416_irq_add(struct device *dev)
|
||||
static int __init s3c2416_irq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
printk(KERN_INFO "S3C2416: IRQ Support\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
|
|||
__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
|
||||
}
|
||||
|
||||
static int s3c2416_pm_add(struct device *dev)
|
||||
static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
pm_cpu_prep = s3c2416_pm_prepare;
|
||||
pm_cpu_sleep = s3c2416_cpu_suspend;
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
|
|||
CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
|
||||
};
|
||||
|
||||
static int s3c2440_clk_add(struct device *dev)
|
||||
static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
struct clk *clock_upll;
|
||||
struct clk *clock_h;
|
||||
|
|
|
|||
|
|
@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
|
|||
},
|
||||
};
|
||||
|
||||
static int __init s3c2440_dma_add(struct device *dev)
|
||||
static int __init s3c2440_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
s3c24xx_dma_order_set(&s3c2440_dma_order);
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
|
|||
.irq_ack = s3c_irq_wdtac97_ack,
|
||||
};
|
||||
|
||||
static int s3c2440_irq_add(struct device *dev)
|
||||
static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
|
|
|
|||
|
|
@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
|
|||
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
|
||||
};
|
||||
|
||||
static int s3c2440_cpufreq_add(struct device *dev)
|
||||
static int s3c2440_cpufreq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
xtal = s3c_cpufreq_clk_get(NULL, "xtal");
|
||||
hclk = s3c_cpufreq_clk_get(NULL, "hclk");
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
|
|||
{ .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
|
||||
};
|
||||
|
||||
static int s3c2440_plls12_add(struct device *dev)
|
||||
static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long xtal;
|
||||
|
|
|
|||
|
|
@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
|
|||
{ .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
|
||||
};
|
||||
|
||||
static int s3c2440_plls169344_add(struct device *dev)
|
||||
static int s3c2440_plls169344_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long xtal;
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
|
|||
},
|
||||
};
|
||||
|
||||
static int s3c2442_clk_add(struct device *dev)
|
||||
static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
struct clk *clock_upll;
|
||||
struct clk *clock_h;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static struct clk clk_arm = {
|
|||
},
|
||||
};
|
||||
|
||||
static int s3c244x_clk_add(struct device *dev)
|
||||
static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
|
||||
unsigned long clkdivn;
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
|
|||
.irq_ack = s3c_irq_cam_ack,
|
||||
};
|
||||
|
||||
static int s3c244x_irq_add(struct device *dev)
|
||||
static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue