mirror of https://gitee.com/openkylin/linux.git
tulip: dmfe: Fix global namespace pollution of phy accessors.
The dmfe driver has "phy_read()" and "phy_write()" functions, which we need to rename because the generic phy layer is about to export generic interfaces with the same name. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
c2c0e8b2b8
commit
73852b2bfb
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@ -328,10 +328,10 @@ static void allocate_rx_buffer(struct net_device *);
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static void update_cr6(u32, void __iomem *);
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static void send_filter_frame(struct DEVICE *);
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static void dm9132_id_table(struct DEVICE *);
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static u16 phy_read(void __iomem *, u8, u8, u32);
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static void phy_write(void __iomem *, u8, u8, u16, u32);
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static void phy_write_1bit(void __iomem *, u32);
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static u16 phy_read_1bit(void __iomem *);
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static u16 dmfe_phy_read(void __iomem *, u8, u8, u32);
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static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32);
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static void dmfe_phy_write_1bit(void __iomem *, u32);
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static u16 dmfe_phy_read_1bit(void __iomem *);
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static u8 dmfe_sense_speed(struct dmfe_board_info *);
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static void dmfe_process_mode(struct dmfe_board_info *);
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static void dmfe_timer(unsigned long);
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@ -770,7 +770,7 @@ static int dmfe_stop(struct DEVICE *dev)
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/* Reset & stop DM910X board */
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dw32(DCR0, DM910X_RESET);
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udelay(100);
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phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
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dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
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/* free interrupt */
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free_irq(db->pdev->irq, dev);
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@ -1154,7 +1154,7 @@ static void dmfe_timer(unsigned long data)
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if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
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db->cr6_data &= ~0x40000;
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update_cr6(db->cr6_data, ioaddr);
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phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
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dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
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db->cr6_data |= 0x40000;
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update_cr6(db->cr6_data, ioaddr);
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db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
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@ -1230,9 +1230,9 @@ static void dmfe_timer(unsigned long data)
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*/
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/* need a dummy read because of PHY's register latch*/
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phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
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link_ok_phy = (phy_read (db->ioaddr,
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db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
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dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
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link_ok_phy = (dmfe_phy_read (db->ioaddr,
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db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
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if (link_ok_phy != link_ok) {
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DMFE_DBUG (0, "PHY and chip report different link status", 0);
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@ -1247,8 +1247,8 @@ static void dmfe_timer(unsigned long data)
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/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
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/* AUTO or force 1M Homerun/Longrun don't need */
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if ( !(db->media_mode & 0x38) )
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phy_write(db->ioaddr, db->phy_addr,
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0, 0x1000, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr,
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0, 0x1000, db->chip_id);
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/* AUTO mode, if INT phyxcer link failed, select EXT device */
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if (db->media_mode & DMFE_AUTO) {
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@ -1649,16 +1649,16 @@ static u8 dmfe_sense_speed(struct dmfe_board_info *db)
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/* CR6 bit18=0, select 10/100M */
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update_cr6(db->cr6_data & ~0x40000, ioaddr);
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phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
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phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
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phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
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phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
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if ( (phy_mode & 0x24) == 0x24 ) {
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if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
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phy_mode = phy_read(db->ioaddr,
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db->phy_addr, 7, db->chip_id) & 0xf000;
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phy_mode = dmfe_phy_read(db->ioaddr,
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db->phy_addr, 7, db->chip_id) & 0xf000;
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else /* DM9102/DM9102A */
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phy_mode = phy_read(db->ioaddr,
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db->phy_addr, 17, db->chip_id) & 0xf000;
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phy_mode = dmfe_phy_read(db->ioaddr,
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db->phy_addr, 17, db->chip_id) & 0xf000;
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switch (phy_mode) {
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case 0x1000: db->op_mode = DMFE_10MHF; break;
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case 0x2000: db->op_mode = DMFE_10MFD; break;
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@ -1695,15 +1695,15 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
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/* DM9009 Chip: Phyxcer reg18 bit12=0 */
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if (db->chip_id == PCI_DM9009_ID) {
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phy_reg = phy_read(db->ioaddr,
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db->phy_addr, 18, db->chip_id) & ~0x1000;
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phy_reg = dmfe_phy_read(db->ioaddr,
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db->phy_addr, 18, db->chip_id) & ~0x1000;
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phy_write(db->ioaddr,
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db->phy_addr, 18, phy_reg, db->chip_id);
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dmfe_phy_write(db->ioaddr,
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db->phy_addr, 18, phy_reg, db->chip_id);
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}
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/* Phyxcer capability setting */
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phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
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phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
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if (db->media_mode & DMFE_AUTO) {
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/* AUTO Mode */
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@ -1724,13 +1724,13 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
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phy_reg|=db->PHY_reg4;
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db->media_mode|=DMFE_AUTO;
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}
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phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
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/* Restart Auto-Negotiation */
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if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
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phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
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if ( !db->chip_type )
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phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
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}
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@ -1762,7 +1762,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
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/* 10/100M phyxcer force mode need */
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if ( !(db->media_mode & 0x18)) {
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/* Forece Mode */
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phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
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phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
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if ( !(phy_reg & 0x1) ) {
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/* parter without N-Way capability */
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phy_reg = 0x0;
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@ -1772,12 +1772,12 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
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case DMFE_100MHF: phy_reg = 0x2000; break;
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case DMFE_100MFD: phy_reg = 0x2100; break;
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}
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phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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dmfe_phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
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mdelay(20);
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phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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dmfe_phy_write(db->ioaddr,
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db->phy_addr, 0, phy_reg, db->chip_id);
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}
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}
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}
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@ -1787,8 +1787,8 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
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* Write a word to Phy register
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*/
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static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
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u16 phy_data, u32 chip_id)
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static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
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u16 phy_data, u32 chip_id)
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{
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u16 i;
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@ -1799,34 +1799,34 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
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/* Send 33 synchronization clock to Phy controller */
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for (i = 0; i < 35; i++)
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phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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/* Send start command(01) to Phy */
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phy_write_1bit(ioaddr, PHY_DATA_0);
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phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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/* Send write command(01) to Phy */
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phy_write_1bit(ioaddr, PHY_DATA_0);
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phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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/* Send Phy address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Send register address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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/* written trasnition */
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phy_write_1bit(ioaddr, PHY_DATA_1);
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phy_write_1bit(ioaddr, PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
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/* Write a word data to PHY controller */
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for ( i = 0x8000; i > 0; i >>= 1)
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phy_write_1bit(ioaddr,
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phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr,
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phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
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}
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}
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@ -1835,7 +1835,7 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
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* Read a word data from phy register
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*/
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static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
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static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
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{
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int i;
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u16 phy_data;
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@ -1848,33 +1848,33 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
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/* Send 33 synchronization clock to Phy controller */
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for (i = 0; i < 35; i++)
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phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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/* Send start command(01) to Phy */
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phy_write_1bit(ioaddr, PHY_DATA_0);
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phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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/* Send read command(10) to Phy */
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phy_write_1bit(ioaddr, PHY_DATA_1);
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phy_write_1bit(ioaddr, PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
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dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
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/* Send Phy address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr,
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phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Send register address */
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for (i = 0x10; i > 0; i = i >> 1)
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phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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dmfe_phy_write_1bit(ioaddr,
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offset & i ? PHY_DATA_1 : PHY_DATA_0);
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/* Skip transition state */
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phy_read_1bit(ioaddr);
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dmfe_phy_read_1bit(ioaddr);
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/* read 16bit data */
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for (phy_data = 0, i = 0; i < 16; i++) {
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phy_data <<= 1;
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phy_data |= phy_read_1bit(ioaddr);
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phy_data |= dmfe_phy_read_1bit(ioaddr);
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}
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}
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@ -1886,7 +1886,7 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
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* Write one bit data to Phy Controller
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*/
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static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
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static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
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{
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dw32(DCR9, phy_data); /* MII Clock Low */
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udelay(1);
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@ -1901,7 +1901,7 @@ static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
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* Read one bit phy data from PHY controller
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*/
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static u16 phy_read_1bit(void __iomem *ioaddr)
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static u16 dmfe_phy_read_1bit(void __iomem *ioaddr)
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{
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u16 phy_data;
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@ -1995,11 +1995,11 @@ static void dmfe_parse_srom(struct dmfe_board_info * db)
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/* Check DM9801 or DM9802 present or not */
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db->HPNA_present = 0;
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update_cr6(db->cr6_data | 0x40000, db->ioaddr);
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tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
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tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
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if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
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/* DM9801 or DM9802 present */
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db->HPNA_timer = 8;
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if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
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if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
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/* DM9801 HomeRun */
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db->HPNA_present = 1;
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dmfe_program_DM9801(db, tmp_reg);
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@ -2025,29 +2025,29 @@ static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
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switch(HPNA_rev) {
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case 0xb900: /* DM9801 E3 */
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db->HPNA_command |= 0x1000;
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reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
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reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
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reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
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reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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break;
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case 0xb901: /* DM9801 E4 */
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reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
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reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
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reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
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reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
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break;
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case 0xb902: /* DM9801 E5 */
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case 0xb903: /* DM9801 E6 */
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default:
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db->HPNA_command |= 0x1000;
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reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
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reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
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reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
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reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
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reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
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break;
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}
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phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
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phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
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phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
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dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
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}
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@ -2060,10 +2060,10 @@ static void dmfe_program_DM9802(struct dmfe_board_info * db)
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uint phy_reg;
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if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
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phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
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phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
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||||
dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
|
||||
phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
|
||||
phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
|
||||
phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
|
||||
dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -2077,7 +2077,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
|
|||
uint phy_reg;
|
||||
|
||||
/* Got remote device status */
|
||||
phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
|
||||
phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
|
||||
switch(phy_reg) {
|
||||
case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
|
||||
case 0x20: phy_reg = 0x0900;break; /* LP/HS */
|
||||
|
|
@ -2087,8 +2087,8 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
|
|||
|
||||
/* Check remote device status match our setting ot not */
|
||||
if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
|
||||
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
|
||||
db->chip_id);
|
||||
dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
|
||||
db->chip_id);
|
||||
db->HPNA_timer=8;
|
||||
} else
|
||||
db->HPNA_timer=600; /* Match, every 10 minutes, check */
|
||||
|
|
|
|||
Loading…
Reference in New Issue