mirror of https://gitee.com/openkylin/linux.git
arm64 fixes:
- Mitigate Spectre-v2 for NVIDIA Denver CPUs - Free memblocks corresponding to freed initrd area -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJa9bgsAAoJELescNyEwWM0yYwIAKvMuUU8d6fy/5EdjTm2uG9p DoSw+ezHeiUrphQwNvOc/fj0vGutM+sftcmghRV1KmP7lvAqk/zvK57PAZjwQ5ua i1X2AJemKr7Gs77FV5Y6Jgkkd2kaIh3n86d9/hM7n9TfAt31vPAYCapb8h3LbRBJ bjZXoTHeujZAIMLGyxzLGVlk9MdW2UjQ3LvWGby/mFEPuktJKkApxBSNQOJOuRKw Ny/eCwFhbyLzDA4zXw7hASld/J+WWBhk0m8ks2qy7BD/F2auZX/p5flU/NoE1VXi JevclGif18iQtZQRV/hJ1woLROfbp6cRKWaVB4cEFKSnB2mG6FLSfrYyvbCj6LE= =lZDP -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: "There's a small memblock accounting problem when freeing the initrd and a Spectre-v2 mitigation for NVIDIA Denver CPUs which just requires a match on the CPU ID register. Summary: - Mitigate Spectre-v2 for NVIDIA Denver CPUs - Free memblocks corresponding to freed initrd area" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: capabilities: Add NVIDIA Denver CPU to bp_harden list arm64: Add MIDR encoding for NVIDIA CPUs arm64: To remove initrd reserved area entry from memblock
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commit
7404bc2773
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@ -75,6 +75,7 @@
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#define ARM_CPU_IMP_CAVIUM 0x43
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_IMP_QCOM 0x51
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#define ARM_CPU_IMP_NVIDIA 0x4E
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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@ -99,6 +100,9 @@
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#define QCOM_CPU_PART_FALKOR 0xC00
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#define QCOM_CPU_PART_KRYO 0x200
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#define NVIDIA_CPU_PART_DENVER 0x003
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#define NVIDIA_CPU_PART_CARMEL 0x004
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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@ -114,6 +118,8 @@
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#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
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#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
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#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
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#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
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#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
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#ifndef __ASSEMBLY__
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@ -316,6 +316,7 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
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{},
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};
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@ -646,8 +646,10 @@ static int keep_initrd __initdata;
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void __init free_initrd_mem(unsigned long start, unsigned long end)
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{
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if (!keep_initrd)
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if (!keep_initrd) {
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free_reserved_area((void *)start, (void *)end, 0, "initrd");
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memblock_free(__virt_to_phys(start), end - start);
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}
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}
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static int __init keepinitrd_setup(char *__unused)
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