mirror of https://gitee.com/openkylin/linux.git
KVM/MIPS32: Arch specific KVM data structures.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sanjay Lal
Ralf Baechle
parent
2235a54dea
commit
740765ce45
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#ifndef __LINUX_KVM_MIPS_H
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#define __LINUX_KVM_MIPS_H
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#include <linux/types.h>
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#define __KVM_MIPS
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#define N_MIPS_COPROC_REGS 32
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#define N_MIPS_COPROC_SEL 8
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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__u32 gprs[32];
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__u32 hi;
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__u32 lo;
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__u32 pc;
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__u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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};
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struct kvm_debug_exit_arch {
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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struct kvm_mips_interrupt {
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/* in */
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__u32 cpu;
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__u32 irq;
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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#endif /* __LINUX_KVM_MIPS_H */
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@ -0,0 +1,667 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#ifndef __MIPS_KVM_HOST_H__
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#define __MIPS_KVM_HOST_H__
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#include <linux/mutex.h>
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#include <linux/hrtimer.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/kvm.h>
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#include <linux/kvm_types.h>
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#define KVM_MAX_VCPUS 1
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#define KVM_USER_MEM_SLOTS 8
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/* memory slots that does not exposed to userspace */
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#define KVM_PRIVATE_MEM_SLOTS 0
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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/* Don't support huge pages */
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#define KVM_HPAGE_GFN_SHIFT(x) 0
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/* We don't currently support large pages. */
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#define KVM_NR_PAGE_SIZES 1
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#define KVM_PAGES_PER_HPAGE(x) 1
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/* Special address that contains the comm page, used for reducing # of traps */
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#define KVM_GUEST_COMMPAGE_ADDR 0x0
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#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
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((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
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#define KVM_GUEST_KUSEG 0x00000000UL
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#define KVM_GUEST_KSEG0 0x40000000UL
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#define KVM_GUEST_KSEG23 0x60000000UL
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#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
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#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
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#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
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#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
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/*
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* Map an address to a certain kernel segment
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*/
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#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
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#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
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#define KVM_INVALID_PAGE 0xdeadbeef
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#define KVM_INVALID_INST 0xdeadbeef
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#define KVM_INVALID_ADDR 0xdeadbeef
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#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
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#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
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#define MS_TO_NS(x) (x * 1E6L)
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#define CAUSEB_DC 27
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#define CAUSEF_DC (_ULCAST_(1) << 27)
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struct kvm;
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struct kvm_run;
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struct kvm_vcpu;
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struct kvm_interrupt;
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extern atomic_t kvm_mips_instance;
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extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
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extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
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extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
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struct kvm_vm_stat {
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u32 remote_tlb_flush;
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};
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struct kvm_vcpu_stat {
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u32 wait_exits;
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u32 cache_exits;
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u32 signal_exits;
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u32 int_exits;
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u32 cop_unusable_exits;
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u32 tlbmod_exits;
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u32 tlbmiss_ld_exits;
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u32 tlbmiss_st_exits;
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u32 addrerr_st_exits;
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u32 addrerr_ld_exits;
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u32 syscall_exits;
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u32 resvd_inst_exits;
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u32 break_inst_exits;
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u32 flush_dcache_exits;
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u32 halt_wakeup;
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};
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enum kvm_mips_exit_types {
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WAIT_EXITS,
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CACHE_EXITS,
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SIGNAL_EXITS,
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INT_EXITS,
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COP_UNUSABLE_EXITS,
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TLBMOD_EXITS,
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TLBMISS_LD_EXITS,
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TLBMISS_ST_EXITS,
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ADDRERR_ST_EXITS,
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ADDRERR_LD_EXITS,
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SYSCALL_EXITS,
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RESVD_INST_EXITS,
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BREAK_INST_EXITS,
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FLUSH_DCACHE_EXITS,
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MAX_KVM_MIPS_EXIT_TYPES
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};
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struct kvm_arch_memory_slot {
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};
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struct kvm_arch {
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/* Guest GVA->HPA page table */
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unsigned long *guest_pmap;
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unsigned long guest_pmap_npages;
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/* Wired host TLB used for the commpage */
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int commpage_tlb;
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};
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#define N_MIPS_COPROC_REGS 32
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#define N_MIPS_COPROC_SEL 8
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struct mips_coproc {
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unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
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#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
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unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
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#endif
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};
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/*
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* Coprocessor 0 register names
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*/
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#define MIPS_CP0_TLB_INDEX 0
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#define MIPS_CP0_TLB_RANDOM 1
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#define MIPS_CP0_TLB_LOW 2
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#define MIPS_CP0_TLB_LO0 2
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#define MIPS_CP0_TLB_LO1 3
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#define MIPS_CP0_TLB_CONTEXT 4
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#define MIPS_CP0_TLB_PG_MASK 5
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#define MIPS_CP0_TLB_WIRED 6
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#define MIPS_CP0_HWRENA 7
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#define MIPS_CP0_BAD_VADDR 8
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#define MIPS_CP0_COUNT 9
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#define MIPS_CP0_TLB_HI 10
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#define MIPS_CP0_COMPARE 11
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#define MIPS_CP0_STATUS 12
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#define MIPS_CP0_CAUSE 13
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#define MIPS_CP0_EXC_PC 14
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#define MIPS_CP0_PRID 15
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#define MIPS_CP0_CONFIG 16
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#define MIPS_CP0_LLADDR 17
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#define MIPS_CP0_WATCH_LO 18
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#define MIPS_CP0_WATCH_HI 19
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#define MIPS_CP0_TLB_XCONTEXT 20
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#define MIPS_CP0_ECC 26
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#define MIPS_CP0_CACHE_ERR 27
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#define MIPS_CP0_TAG_LO 28
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#define MIPS_CP0_TAG_HI 29
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#define MIPS_CP0_ERROR_PC 30
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#define MIPS_CP0_DEBUG 23
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#define MIPS_CP0_DEPC 24
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#define MIPS_CP0_PERFCNT 25
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#define MIPS_CP0_ERRCTL 26
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#define MIPS_CP0_DATA_LO 28
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#define MIPS_CP0_DATA_HI 29
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#define MIPS_CP0_DESAVE 31
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#define MIPS_CP0_CONFIG_SEL 0
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#define MIPS_CP0_CONFIG1_SEL 1
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#define MIPS_CP0_CONFIG2_SEL 2
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#define MIPS_CP0_CONFIG3_SEL 3
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/* Config0 register bits */
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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#define CP0C0_AR 10
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#define CP0C0_MT 7
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#define CP0C0_VI 3
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#define CP0C0_K0 0
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/* Config1 register bits */
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#define CP0C1_M 31
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#define CP0C1_MMU 25
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#define CP0C1_IS 22
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#define CP0C1_IL 19
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#define CP0C1_IA 16
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#define CP0C1_DS 13
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#define CP0C1_DL 10
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#define CP0C1_DA 7
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#define CP0C1_C2 6
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#define CP0C1_MD 5
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#define CP0C1_PC 4
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#define CP0C1_WR 3
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#define CP0C1_CA 2
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#define CP0C1_EP 1
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#define CP0C1_FP 0
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/* Config2 Register bits */
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#define CP0C2_M 31
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#define CP0C2_TU 28
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#define CP0C2_TS 24
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#define CP0C2_TL 20
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#define CP0C2_TA 16
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#define CP0C2_SU 12
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#define CP0C2_SS 8
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#define CP0C2_SL 4
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#define CP0C2_SA 0
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/* Config3 Register bits */
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#define CP0C3_M 31
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#define CP0C3_ISA_ON_EXC 16
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#define CP0C3_ULRI 13
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#define CP0C3_DSPP 10
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#define CP0C3_LPA 7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP 4
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#define CP0C3_MT 2
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#define CP0C3_SM 1
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#define CP0C3_TL 0
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/* Have config1, Cacheable, noncoherent, write-back, write allocate*/
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x3 << CP0C0_K0))
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU, no watch registers */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),
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no external interrupt controller, no vectored interrupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_SM) | (0 << CP0C3_TL))
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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enum mips_mmu_types {
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MMU_TYPE_NONE,
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MMU_TYPE_R4000,
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MMU_TYPE_RESERVED,
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MMU_TYPE_FMT,
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MMU_TYPE_R3000,
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MMU_TYPE_R6000,
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MMU_TYPE_R8000
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};
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/*
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* Trap codes
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*/
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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/*
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* Trap definitions added for r4000 port.
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*/
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency exception */
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#define T_FPE 15 /* Floating point exception */
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#define T_WATCH 23 /* Watch address reference */
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#define T_VCED 31 /* Virtual coherency data */
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/* Resume Flags */
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#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
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#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
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#define RESUME_GUEST 0
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#define RESUME_GUEST_DR RESUME_FLAG_DR
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#define RESUME_HOST RESUME_FLAG_HOST
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enum emulation_result {
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EMULATE_DONE, /* no further processing */
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EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
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EMULATE_FAIL, /* can't emulate this instruction */
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EMULATE_WAIT, /* WAIT instruction */
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EMULATE_PRIV_FAIL,
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};
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#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
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#define MIPS3_PG_V 0x00000002 /* Valid */
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#define MIPS3_PG_NV 0x00000000
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#define MIPS3_PG_D 0x00000004 /* Dirty */
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#define mips3_paddr_to_tlbpfn(x) \
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(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_tlbpfn_to_paddr(x) \
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((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
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#define MIPS3_PG_SHIFT 6
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#define MIPS3_PG_FRAME 0x3fffffc0
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#define VPN2_MASK 0xffffe000
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#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
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#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
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#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
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#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
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struct kvm_mips_tlb {
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long tlb_mask;
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long tlb_hi;
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long tlb_lo0;
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long tlb_lo1;
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};
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#define KVM_MIPS_GUEST_TLB_SIZE 64
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struct kvm_vcpu_arch {
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void *host_ebase, *guest_ebase;
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unsigned long host_stack;
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unsigned long host_gp;
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/* Host CP0 registers used when handling exits from guest */
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unsigned long host_cp0_badvaddr;
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unsigned long host_cp0_cause;
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unsigned long host_cp0_epc;
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unsigned long host_cp0_entryhi;
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uint32_t guest_inst;
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/* GPRS */
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unsigned long gprs[32];
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unsigned long hi;
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unsigned long lo;
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unsigned long pc;
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/* FPU State */
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struct mips_fpu_struct fpu;
|
||||
|
||||
/* COP0 State */
|
||||
struct mips_coproc *cop0;
|
||||
|
||||
/* Host KSEG0 address of the EI/DI offset */
|
||||
void *kseg0_commpage;
|
||||
|
||||
u32 io_gpr; /* GPR used as IO source/target */
|
||||
|
||||
/* Used to calibrate the virutal count register for the guest */
|
||||
int32_t host_cp0_count;
|
||||
|
||||
/* Bitmask of exceptions that are pending */
|
||||
unsigned long pending_exceptions;
|
||||
|
||||
/* Bitmask of pending exceptions to be cleared */
|
||||
unsigned long pending_exceptions_clr;
|
||||
|
||||
unsigned long pending_load_cause;
|
||||
|
||||
/* Save/Restore the entryhi register when are are preempted/scheduled back in */
|
||||
unsigned long preempt_entryhi;
|
||||
|
||||
/* S/W Based TLB for guest */
|
||||
struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
|
||||
|
||||
/* Cached guest kernel/user ASIDs */
|
||||
uint32_t guest_user_asid[NR_CPUS];
|
||||
uint32_t guest_kernel_asid[NR_CPUS];
|
||||
struct mm_struct guest_kernel_mm, guest_user_mm;
|
||||
|
||||
struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
|
||||
|
||||
|
||||
struct hrtimer comparecount_timer;
|
||||
|
||||
int last_sched_cpu;
|
||||
|
||||
/* WAIT executed */
|
||||
int wait;
|
||||
};
|
||||
|
||||
|
||||
#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
|
||||
#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
|
||||
#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
|
||||
#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
|
||||
#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
|
||||
#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
|
||||
#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
|
||||
#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
|
||||
#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
|
||||
#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
|
||||
#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
|
||||
#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
|
||||
#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
|
||||
#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
|
||||
#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
|
||||
#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
|
||||
#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
|
||||
#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
|
||||
#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
|
||||
#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
|
||||
#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
|
||||
#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
|
||||
#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
|
||||
#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
|
||||
#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
|
||||
#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
|
||||
#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
|
||||
#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
|
||||
#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
|
||||
#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
|
||||
#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
|
||||
#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
|
||||
#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
|
||||
#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
|
||||
#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
|
||||
#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
|
||||
#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
|
||||
#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
|
||||
#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
|
||||
#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
|
||||
#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
|
||||
#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
|
||||
#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
|
||||
|
||||
#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
|
||||
#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
|
||||
#define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
|
||||
#define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
|
||||
#define kvm_change_c0_guest_cause(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_cause(cop0, change); \
|
||||
kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
|
||||
}
|
||||
#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
|
||||
#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
|
||||
#define kvm_change_c0_guest_ebase(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_ebase(cop0, change); \
|
||||
kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
|
||||
}
|
||||
|
||||
|
||||
struct kvm_mips_callbacks {
|
||||
int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_syscall) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_res_inst) (struct kvm_vcpu *vcpu);
|
||||
int (*handle_break) (struct kvm_vcpu *vcpu);
|
||||
int (*vm_init) (struct kvm *kvm);
|
||||
int (*vcpu_init) (struct kvm_vcpu *vcpu);
|
||||
int (*vcpu_setup) (struct kvm_vcpu *vcpu);
|
||||
gpa_t(*gva_to_gpa) (gva_t gva);
|
||||
void (*queue_timer_int) (struct kvm_vcpu *vcpu);
|
||||
void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
|
||||
void (*queue_io_int) (struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq);
|
||||
void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_interrupt *irq);
|
||||
int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
uint32_t cause);
|
||||
int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
|
||||
uint32_t cause);
|
||||
int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu,
|
||||
struct kvm_regs *regs);
|
||||
int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu,
|
||||
struct kvm_regs *regs);
|
||||
};
|
||||
extern struct kvm_mips_callbacks *kvm_mips_callbacks;
|
||||
int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
|
||||
|
||||
/* Debug: dump vcpu state */
|
||||
int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
|
||||
|
||||
/* Trampoline ASM routine to start running in "Guest" context */
|
||||
extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
|
||||
|
||||
/* TLB handling */
|
||||
uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
|
||||
|
||||
uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
|
||||
|
||||
uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
|
||||
|
||||
extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
|
||||
struct kvm_mips_tlb *tlb,
|
||||
unsigned long *hpa0,
|
||||
unsigned long *hpa1);
|
||||
|
||||
extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern void kvm_mips_dump_host_tlbs(void);
|
||||
extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_mips_flush_host_tlb(int skip_kseg0);
|
||||
extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
|
||||
extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
|
||||
|
||||
extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
|
||||
unsigned long entryhi);
|
||||
extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
|
||||
extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
|
||||
unsigned long gva);
|
||||
extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
|
||||
struct kvm_vcpu *vcpu);
|
||||
extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_local_flush_tlb_all(void);
|
||||
extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
|
||||
extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
|
||||
extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
|
||||
|
||||
/* Emulation */
|
||||
uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
|
||||
enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
|
||||
struct kvm_run *run);
|
||||
|
||||
enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
|
||||
|
||||
enum emulation_result kvm_mips_check_privilege(unsigned long cause,
|
||||
uint32_t *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
|
||||
uint32_t *opc,
|
||||
uint32_t cause,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
|
||||
uint32_t *opc,
|
||||
uint32_t cause,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
enum emulation_result kvm_mips_emulate_store(uint32_t inst,
|
||||
uint32_t cause,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
enum emulation_result kvm_mips_emulate_load(uint32_t inst,
|
||||
uint32_t cause,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
/* Dynamic binary translation */
|
||||
extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
|
||||
struct kvm_vcpu *vcpu);
|
||||
extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
|
||||
struct kvm_vcpu *vcpu);
|
||||
extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
|
||||
struct kvm_vcpu *vcpu);
|
||||
extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
|
||||
struct kvm_vcpu *vcpu);
|
||||
|
||||
/* Misc */
|
||||
extern void mips32_SyncICache(unsigned long addr, unsigned long size);
|
||||
extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
|
||||
extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
|
||||
|
||||
|
||||
#endif /* __MIPS_KVM_HOST_H__ */
|
||||
Loading…
Reference in New Issue