mirror of https://gitee.com/openkylin/linux.git
arm64: tegra: Add Tegra210 support
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
0f279ebdf3
commit
742af7e7a0
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra210-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nvidia,tegra210";
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interrupt-parent = <&lic>;
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#address-cells = <2>;
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#size-cells = <2>;
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host1x@0,50000000 {
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compatible = "nvidia,tegra210-host1x", "simple-bus";
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reg = <0x0 0x50000000 0x0 0x00034000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
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dpaux1: dpaux@0,54040000 {
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compatible = "nvidia,tegra210-dpaux";
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reg = <0x0 0x54040000 0x0 0x00040000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
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<&tegra_car TEGRA210_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 207>;
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reset-names = "dpaux";
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status = "disabled";
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};
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vi@0,54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x0 0x54080000 0x0 0x00040000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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tsec@0,54100000 {
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compatible = "nvidia,tegra210-tsec";
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reg = <0x0 0x54100000 0x0 0x00040000>;
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};
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dc@0,54200000 {
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compatible = "nvidia,tegra210-dc";
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reg = <0x0 0x54200000 0x0 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DISP1>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DC>;
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nvidia,head = <0>;
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};
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dc@0,54240000 {
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compatible = "nvidia,tegra210-dc";
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reg = <0x0 0x54240000 0x0 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DISP2>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DCB>;
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nvidia,head = <1>;
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};
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dsi@0,54300000 {
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compatible = "nvidia,tegra210-dsi";
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reg = <0x0 0x54300000 0x0 0x00040000>;
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clocks = <&tegra_car TEGRA210_CLK_DSIA>,
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<&tegra_car TEGRA210_CLK_DSIALP>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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vic@0,54340000 {
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compatible = "nvidia,tegra210-vic";
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reg = <0x0 0x54340000 0x0 0x00040000>;
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status = "disabled";
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};
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nvjpg@0,54380000 {
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compatible = "nvidia,tegra210-nvjpg";
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reg = <0x0 0x54380000 0x0 0x00040000>;
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status = "disabled";
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};
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dsi@0,54400000 {
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compatible = "nvidia,tegra210-dsi";
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reg = <0x0 0x54400000 0x0 0x00040000>;
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clocks = <&tegra_car TEGRA210_CLK_DSIB>,
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<&tegra_car TEGRA210_CLK_DSIBLP>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 82>;
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reset-names = "dsi";
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nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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nvdec@0,54480000 {
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compatible = "nvidia,tegra210-nvdec";
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reg = <0x0 0x54480000 0x0 0x00040000>;
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status = "disabled";
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};
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nvenc@0,544c0000 {
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compatible = "nvidia,tegra210-nvenc";
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reg = <0x0 0x544c0000 0x0 0x00040000>;
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status = "disabled";
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};
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tsec@0,54500000 {
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compatible = "nvidia,tegra210-tsec";
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reg = <0x0 0x54500000 0x0 0x00040000>;
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status = "disabled";
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};
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sor@0,54540000 {
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compatible = "nvidia,tegra210-sor";
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reg = <0x0 0x54540000 0x0 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SOR0>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_DP>,
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<&tegra_car TEGRA210_CLK_SOR_SAFE>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 182>;
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reset-names = "sor";
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status = "disabled";
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};
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sor@0,54580000 {
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compatible = "nvidia,tegra210-sor1";
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reg = <0x0 0x54580000 0x0 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SOR1>,
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<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_DP>,
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<&tegra_car TEGRA210_CLK_SOR_SAFE>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 183>;
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reset-names = "sor";
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status = "disabled";
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};
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dpaux: dpaux@0,545c0000 {
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compatible = "nvidia,tegra124-dpaux";
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reg = <0x0 0x545c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
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<&tegra_car TEGRA210_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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status = "disabled";
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};
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isp@0,54600000 {
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compatible = "nvidia,tegra210-isp";
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reg = <0x0 0x54600000 0x0 0x00040000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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isp@0,54680000 {
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compatible = "nvidia,tegra210-isp";
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reg = <0x0 0x54680000 0x0 0x00040000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c@0,546c0000 {
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compatible = "nvidia,tegra210-i2c-vi";
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reg = <0x0 0x546c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@0,50041000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x50041000 0x0 0x1000>,
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<0x0 0x50042000 0x0 0x2000>,
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<0x0 0x50044000 0x0 0x2000>,
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<0x0 0x50046000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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gpu@0,57000000 {
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compatible = "nvidia,gm20b";
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reg = <0x0 0x57000000 0x0 0x01000000>,
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<0x0 0x58000000 0x0 0x01000000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&tegra_car TEGRA210_CLK_GPU>,
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<&tegra_car TEGRA210_CLK_PLL_P_OUT5>;
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clock-names = "gpu", "pwr";
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resets = <&tegra_car 184>;
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reset-names = "gpu";
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status = "disabled";
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};
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lic: interrupt-controller@0,60004000 {
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compatible = "nvidia,tegra210-ictlr";
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reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
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<0x0 0x60004100 0x0 0x40>, /* secondary controller */
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<0x0 0x60004200 0x0 0x40>, /* tertiary controller */
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<0x0 0x60004300 0x0 0x40>, /* quaternary controller */
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<0x0 0x60004400 0x0 0x40>, /* quinary controller */
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<0x0 0x60004500 0x0 0x40>; /* senary controller */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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timer@0,60005000 {
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compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
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reg = <0x0 0x60005000 0x0 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TIMER>;
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clock-names = "timer";
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};
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tegra_car: clock@0,60006000 {
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compatible = "nvidia,tegra210-car";
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reg = <0x0 0x60006000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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flow-controller@0,60007000 {
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compatible = "nvidia,tegra210-flowctrl";
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reg = <0x0 0x60007000 0x0 0x1000>;
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};
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gpio: gpio@0,6000d000 {
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compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
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reg = <0x0 0x6000d000 0x0 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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apbdma: dma@0,60020000 {
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compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x0 0x60020000 0x0 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
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clock-names = "dma";
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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apbmisc@0,70000800 {
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compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
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reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
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<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
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};
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pinmux: pinmux@0,700008d4 {
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compatible = "nvidia,tegra210-pinmux";
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reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
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<0x0 0x70003000 0x0 0x294>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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*/
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uarta: serial@0,70006000 {
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compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_UARTA>;
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clock-names = "serial";
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartb: serial@0,70006040 {
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compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006040 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_UARTB>;
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clock-names = "serial";
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartc: serial@0,70006200 {
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compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006200 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_UARTC>;
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clock-names = "serial";
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@0,7000a000 {
|
||||
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c000 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C1>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 12>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 21>, <&apbdma 21>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c400 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c400 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C2>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 54>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 22>, <&apbdma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c500 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C3>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 67>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 23>, <&apbdma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c700 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c700 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C4>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 103>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 26>, <&apbdma 26>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d000 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C5>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 47>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 24>, <&apbdma 24>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d100 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d100 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C6>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 166>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 30>, <&apbdma 30>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d400 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 41>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 15>, <&apbdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d600 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 44>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d800 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d800 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 46>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 17>, <&apbdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000da00 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000da00 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 68>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 18>, <&apbdma 18>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@0,7000e000 {
|
||||
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x0 0x7000e000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
pmc: pmc@0,7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
fuse@0,7000f800 {
|
||||
compatible = "nvidia,tegra210-efuse";
|
||||
reg = <0x0 0x7000f800 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
mc: memory-controller@0,70019000 {
|
||||
compatible = "nvidia,tegra210-mc";
|
||||
reg = <0x0 0x70019000 0x0 0x1000>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_MC>;
|
||||
clock-names = "mc";
|
||||
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
hda@0,70030000 {
|
||||
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
|
||||
reg = <0x0 0x70030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_HDA>,
|
||||
<&tegra_car TEGRA210_CLK_HDA2HDMI>,
|
||||
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
|
||||
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
resets = <&tegra_car 125>, /* hda */
|
||||
<&tegra_car 128>, /* hda2hdmi */
|
||||
<&tegra_car 111>; /* hda2codec_2x */
|
||||
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0200 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0200 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 9>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0400 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0600 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mipi: mipi@0,700e3000 {
|
||||
compatible = "nvidia,tegra210-mipi";
|
||||
reg = <0x0 0x700e3000 0x0 0x100>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
|
||||
clock-names = "mipi-cal";
|
||||
#nvidia,mipi-calibrate-cells = <1>;
|
||||
};
|
||||
|
||||
spi@0,70410000 {
|
||||
compatible = "nvidia,tegra210-qspi";
|
||||
reg = <0x0 0x70410000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_QSPI>;
|
||||
clock-names = "qspi";
|
||||
resets = <&tegra_car 211>;
|
||||
reset-names = "qspi";
|
||||
dmas = <&apbdma 5>, <&apbdma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d000000 {
|
||||
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 22>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy1: usb-phy@0,7d000000 {
|
||||
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USBD>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 22>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
nvidia,has-utmi-pad-registers;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d004000 {
|
||||
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USB2>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 58>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy2: usb-phy@0,7d004000 {
|
||||
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USB2>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue