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openrisc: tlb miss handler optimizations
By slightly reorganizing the code, the number of registers used in the tlb miss handlers can be reduced by two, thus removing the need to save them to memory. Also, some dead and commented out code is removed. No functional change. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Signed-off-by: Jonas Bonn <jonas@southpole.se> Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stefan Kristiansson
Stafford Horne
parent
3e06a16339
commit
742fb582b4
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@ -971,8 +971,6 @@ ENTRY(dtlb_miss_handler)
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EXCEPTION_STORE_GPR2
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EXCEPTION_STORE_GPR3
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EXCEPTION_STORE_GPR4
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EXCEPTION_STORE_GPR5
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EXCEPTION_STORE_GPR6
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/*
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* get EA of the miss
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*/
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@ -980,91 +978,70 @@ ENTRY(dtlb_miss_handler)
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/*
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* pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
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*/
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GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
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GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
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l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
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l.slli r4,r4,0x2 // to get address << 2
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l.add r5,r4,r3 // r4 is pgd_index(daddr)
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l.add r3,r4,r3 // r4 is pgd_index(daddr)
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/*
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* if (pmd_none(*pmd))
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* goto pmd_none:
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*/
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tophys (r4,r5)
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tophys (r4,r3)
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l.lwz r3,0x0(r4) // get *pmd value
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l.sfne r3,r0
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l.bnf d_pmd_none
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l.andi r3,r3,~PAGE_MASK //0x1fff // ~PAGE_MASK
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/*
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* if (pmd_bad(*pmd))
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* pmd_clear(pmd)
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* goto pmd_bad:
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*/
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// l.sfeq r3,r0 // check *pmd value
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// l.bf d_pmd_good
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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// l.j d_pmd_bad
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// l.sw 0x0(r4),r0 // clear pmd
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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d_pmd_good:
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/*
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* pte = *pte_offset(pmd, daddr);
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*/
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l.lwz r4,0x0(r4) // get **pmd value
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l.and r4,r4,r3 // & PAGE_MASK
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l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
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l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
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l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
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l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
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l.slli r3,r3,0x2 // to get address << 2
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l.add r3,r3,r4
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l.lwz r2,0x0(r3) // this is pte at last
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l.lwz r3,0x0(r3) // this is pte at last
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/*
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* if (!pte_present(pte))
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*/
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l.andi r4,r2,0x1
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l.andi r4,r3,0x1
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l.sfne r4,r0 // is pte present
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l.bnf d_pte_not_present
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l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
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l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
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/*
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* fill DTLB TR register
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*/
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l.and r4,r2,r3 // apply the mask
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l.and r4,r3,r4 // apply the mask
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// Determine number of DMMU sets
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l.mfspr r6, r0, SPR_DMMUCFGR
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l.andi r6, r6, SPR_DMMUCFGR_NTS
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l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
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l.mfspr r2, r0, SPR_DMMUCFGR
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l.andi r2, r2, SPR_DMMUCFGR_NTS
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l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
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l.ori r3, r0, 0x1
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l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
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l.addi r6, r3, -1 // r6 = nsets mask
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l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
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l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
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l.addi r2, r3, -1 // r2 = nsets mask
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l.mfspr r3, r0, SPR_EEAR_BASE
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l.srli r3, r3, 0xd // >> PAGE_SHIFT
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l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
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//NUM_TLB_ENTRIES
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l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
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l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
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/*
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* fill DTLB MR register
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*/
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l.mfspr r2,r0,SPR_EEAR_BASE
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
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l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
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l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
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l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
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l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
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l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.rfe
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d_pmd_bad:
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l.nop 1
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.rfe
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d_pmd_none:
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d_pte_not_present:
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
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/* ==============================================[ ITLB miss handler ]=== */
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@ -1072,8 +1049,6 @@ ENTRY(itlb_miss_handler)
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EXCEPTION_STORE_GPR2
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EXCEPTION_STORE_GPR3
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EXCEPTION_STORE_GPR4
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EXCEPTION_STORE_GPR5
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EXCEPTION_STORE_GPR6
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/*
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* get EA of the miss
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*/
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@ -1083,30 +1058,19 @@ ENTRY(itlb_miss_handler)
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* pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
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*
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*/
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GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
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GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
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l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
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l.slli r4,r4,0x2 // to get address << 2
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l.add r5,r4,r3 // r4 is pgd_index(daddr)
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l.add r3,r4,r3 // r4 is pgd_index(daddr)
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/*
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* if (pmd_none(*pmd))
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* goto pmd_none:
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*/
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tophys (r4,r5)
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tophys (r4,r3)
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l.lwz r3,0x0(r4) // get *pmd value
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l.sfne r3,r0
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l.bnf i_pmd_none
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l.andi r3,r3,0x1fff // ~PAGE_MASK
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/*
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* if (pmd_bad(*pmd))
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* pmd_clear(pmd)
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* goto pmd_bad:
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*/
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// l.sfeq r3,r0 // check *pmd value
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// l.bf i_pmd_good
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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// l.j i_pmd_bad
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// l.sw 0x0(r4),r0 // clear pmd
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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i_pmd_good:
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/*
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@ -1115,35 +1079,36 @@ i_pmd_good:
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*/
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l.lwz r4,0x0(r4) // get **pmd value
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l.and r4,r4,r3 // & PAGE_MASK
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l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
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l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
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l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
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l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
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l.slli r3,r3,0x2 // to get address << 2
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l.add r3,r3,r4
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l.lwz r2,0x0(r3) // this is pte at last
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l.lwz r3,0x0(r3) // this is pte at last
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/*
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* if (!pte_present(pte))
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*
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*/
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l.andi r4,r2,0x1
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l.andi r4,r3,0x1
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l.sfne r4,r0 // is pte present
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l.bnf i_pte_not_present
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l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
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l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
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/*
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* fill ITLB TR register
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*/
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l.and r4,r2,r3 // apply the mask
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l.andi r3,r2,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
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// l.andi r3,r2,0x400 // _PAGE_EXEC
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l.and r4,r3,r4 // apply the mask
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l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
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l.sfeq r3,r0
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l.bf itlb_tr_fill //_workaround
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// Determine number of IMMU sets
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l.mfspr r6, r0, SPR_IMMUCFGR
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l.andi r6, r6, SPR_IMMUCFGR_NTS
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l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
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l.mfspr r2, r0, SPR_IMMUCFGR
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l.andi r2, r2, SPR_IMMUCFGR_NTS
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l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
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l.ori r3, r0, 0x1
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l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
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l.addi r6, r3, -1 // r6 = nsets mask
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l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
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l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
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l.addi r2, r3, -1 // r2 = nsets mask
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l.mfspr r3, r0, SPR_EEAR_BASE
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l.srli r3, r3, 0xd // >> PAGE_SHIFT
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l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
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/*
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* __PHX__ :: fixme
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@ -1155,38 +1120,24 @@ i_pmd_good:
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itlb_tr_fill_workaround:
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l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
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itlb_tr_fill:
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l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
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l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
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/*
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* fill DTLB MR register
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*/
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l.mfspr r2,r0,SPR_EEAR_BASE
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l.addi r3,r0,0xffffe000 // PAGE_MASK
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l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
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l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
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l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
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l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
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l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
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l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.rfe
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i_pmd_bad:
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l.nop 1
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.rfe
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i_pmd_none:
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i_pte_not_present:
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EXCEPTION_LOAD_GPR2
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EXCEPTION_LOAD_GPR3
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
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/* ==============================================[ boot tlb handlers ]=== */
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