mirror of https://gitee.com/openkylin/linux.git
staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
Driver probe function is a mess and shall be refactored a lot. At first make use of assert and deassert control factoring out a new function called 'mt7621_pcie_enable_port'. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c8242bef7c
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@ -480,6 +480,39 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
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return 0;
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}
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static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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struct device *dev = pcie->dev;
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u32 slot = port->slot;
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u32 val = 0;
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int err;
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err = clk_prepare_enable(port->pcie_clk);
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if (err) {
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dev_err(dev, "failed to enable pcie%d clock\n", slot);
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return err;
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}
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reset_control_assert(port->pcie_rst);
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reset_control_deassert(port->pcie_rst);
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if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
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reset_control_assert(port->pcie_rst);
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rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
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pcie_link_status &= ~(1 << slot);
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} else {
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pcie_link_status |= BIT(slot);
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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/* enable pcie interrupt */
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val |= BIT(20 + slot);
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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}
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return 0;
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}
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static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
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struct list_head *res)
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{
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@ -518,6 +551,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct mt7621_pcie *pcie;
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struct pci_host_bridge *bridge;
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struct mt7621_pcie_port *port, *tmp;
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int err;
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u32 val = 0;
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LIST_HEAD(res);
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@ -546,12 +580,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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ioport_resource.start = 0;
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ioport_resource.end = ~0UL; /* no limit */
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val = RALINK_PCIE0_RST;
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val |= RALINK_PCIE1_RST;
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val |= RALINK_PCIE2_RST;
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ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
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*(unsigned int *)(0xbe000060) &= ~(0x3 << 10 | 0x3 << 3);
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*(unsigned int *)(0xbe000060) |= BIT(10) | BIT(3);
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mdelay(100);
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@ -561,11 +589,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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mdelay(100);
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val = RALINK_PCIE0_RST;
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val |= RALINK_PCIE1_RST;
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val |= RALINK_PCIE2_RST;
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DEASSERT_SYSRST_PCIE(val);
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list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
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err = mt7621_pcie_enable_port(port);
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if (err) {
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dev_err(dev, "enabling port %d failed\n", port->slot);
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list_del(&port->list);
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}
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}
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if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2
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bypass_pipe_rst(pcie);
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@ -591,42 +621,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7); // set DATA
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mdelay(1000);
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if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
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printk("PCIE0 no card, disable it(RST&CLK)\n");
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ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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pcie_link_status &= ~(BIT(0));
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} else {
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pcie_link_status |= BIT(0);
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= BIT(20); // enable pcie1 interrupt
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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}
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if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
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printk("PCIE1 no card, disable it(RST&CLK)\n");
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ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
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rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
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pcie_link_status &= ~(BIT(1));
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} else {
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pcie_link_status |= BIT(1);
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= BIT(21); // enable pcie1 interrupt
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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}
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if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
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printk("PCIE2 no card, disable it(RST&CLK)\n");
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ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
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rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
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pcie_link_status &= ~(BIT(2));
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} else {
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pcie_link_status |= BIT(2);
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= BIT(22); // enable pcie2 interrupt
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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}
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if (pcie_link_status == 0)
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return 0;
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