mirror of https://gitee.com/openkylin/linux.git
dt-bindings: dp83867: Convert DP83867 to yaml
Convert the dp83867 binding to yaml. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Dan Murphy
David S. Miller
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e90b651e7b
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* Texas Instruments - dp83867 Giga bit ethernet phy
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
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Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
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will be left at their default values, as set by the PHY's pin strapping.
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The default strapping will use a delay of 2.00 ns. Thus
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PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
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internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
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should use "rgmii-id" if internal delays are desired as this may be
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changed in future to cause "rgmii" mode to disable delays.
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Optional property:
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- ti,min-output-impedance - MAC Interface Impedance control to set
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the programmable output impedance to
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minimum value (35 ohms).
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- ti,max-output-impedance - MAC Interface Impedance control to set
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the programmable output impedance to
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maximum value (70 ohms).
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- ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
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board has RX_DV/RX_CTRL pin strapped in
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mode 1 or 2. To ensure PHY operation,
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there are specific actions that
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software needs to take when this pin is
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strapped in these modes. See data manual
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for details.
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- ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
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for applicable values. The CLK_OUT pin can also
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be disabled by this property. When omitted, the
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PHY's default will be left as is.
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- ti,sgmii-ref-clock-output-enable - This denotes which
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SGMII configuration is used (4 or 6-wire modes).
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Some MACs work with differential SGMII clock.
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See data manual for details.
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values (deprecated)
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-tx-fifo-depth - As defined in the ethernet-controller.yaml. Values for
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the depth can be found in dt-bindings/net/ti-dp83867.h
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-rx-fifo-depth - As defined in the ethernet-controller.yaml. Values for
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the depth can be found in dt-bindings/net/ti-dp83867.h
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Note: ti,min-output-impedance and ti,max-output-impedance are mutually
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exclusive. When both properties are present ti,max-output-impedance
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takes precedence.
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Default child nodes are standard Ethernet PHY device
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nodes as described in Documentation/devicetree/bindings/net/phy.txt
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Example:
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ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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Datasheet can be found:
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http://www.ti.com/product/DP83867IR/datasheet
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@ -0,0 +1,127 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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# Copyright (C) 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: TI DP83867 ethernet PHY
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allOf:
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- $ref: "ethernet-controller.yaml#"
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maintainers:
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- Dan Murphy <dmurphy@ti.com>
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description: |
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The DP83867 device is a robust, low power, fully featured Physical Layer
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transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
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and 1000BASE-T Ethernet protocols.
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The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
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LANs. It interfaces directly to twisted pair media via an external
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transformer. This device interfaces directly to the MAC layer through the
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IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
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Media Independent Interface (GMII) or Reduced GMII (RGMII).
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Specifications about the charger can be found at:
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https://www.ti.com/lit/gpn/dp83867ir
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properties:
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reg:
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maxItems: 1
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ti,min-output-impedance:
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type: boolean
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description: |
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MAC Interface Impedance control to set the programmable output impedance
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to a minimum value (35 ohms).
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ti,max-output-impedance:
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type: boolean
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description: |
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MAC Interface Impedance control to set the programmable output impedance
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to a maximum value (70 ohms).
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Note: ti,min-output-impedance and ti,max-output-impedance are mutually
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exclusive. When both properties are present ti,max-output-impedance
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takes precedence.
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tx-fifo-depth:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
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rx-fifo-depth:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
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ti,clk-output-sel:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
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for applicable values. The CLK_OUT pin can also be disabled by this
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property. When omitted, the PHY's default will be left as is.
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ti,rx-internal-delay:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
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ti,tx-internal-delay:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.
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Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock
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delays will be left at their default values, as set by the PHY's pin
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strapping. The default strapping will use a delay of 2.00 ns. Thus
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PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
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internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
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should use "rgmii-id" if internal delays are desired as this may be
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changed in future to cause "rgmii" mode to disable delays.
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ti,dp83867-rxctrl-strap-quirk:
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type: boolean
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description: |
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This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
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mode 1 or 2. To ensure PHY operation, there are specific actions that
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software needs to take when this pin is strapped in these modes.
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See data manual for details.
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ti,sgmii-ref-clock-output-enable:
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type: boolean
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description: |
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This denotes which SGMII configuration is used (4 or 6-wire modes).
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Some MACs work with differential SGMII clock. See data manual for details.
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ti,fifo-depth:
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deprecated: true
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
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values.
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required:
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- reg
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examples:
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- |
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#include <dt-bindings/net/ti-dp83867.h>
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,max-output-impedance;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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};
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};
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