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Amlogic 64-bit DT updates for v4.16, round 2 

- clock, pinctrl, PWM and reset nodes for new AXG SoC family
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Merge tag 'amlogic-dt64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Pull "Amlogic 64-bit DT updates for v4.16, round 2" from Kevin Hilman:

This adds a few more basics (clock, pinctrl, PWM, reset) for the new AXG
family of Amlogic SoCs.

* tag 'amlogic-dt64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson-axg: add new reset DT node
  ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC
  ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
  documentation: Add compatibles for Amlogic Meson AXG pin controllers
  arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
This commit is contained in:
Arnd Bergmann 2018-01-05 12:28:48 +01:00
parent e4ccf203ff 43b9f617b5
commit 7598a4e035
2 changed files with 177 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
View File

@ -9,6 +9,8 @@ Required properties for the root node:
"amlogic,meson-gxbb-aobus-pinctrl"
"amlogic,meson-gxl-periphs-pinctrl"
"amlogic,meson-gxl-aobus-pinctrl"
"amlogic,meson-axg-periphs-pinctrl"
"amlogic,meson-axg-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===

175
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -120,6 +120,26 @@ cbus: bus@ffd00000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
pwm_ab: pwm@1b000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1b000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@1a000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1a000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
reset: reset-controller@1004 {
compatible = "amlogic,meson-axg-reset";
reg = <0x0 0x01004 0x0 0x9c>;
#reset-cells = <1>;
};
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x24000 0x0 0x14>;
@ -148,6 +168,20 @@ gic: interrupt-controller@ffc01000 {
#address-cells = <0>;
};
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
clkc: clock-controller@0 {
compatible = "amlogic,axg-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x320>;
};
};
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
@ -157,6 +191,116 @@ mailbox: mailbox@ff63dc00 {
#mbox-cells = <1>;
};
periphs: periphs@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@480 {
reg = <0x0 0x00480 0x0 0x40>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x3c>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
pwm_a_a_pins: pwm_a_a {
mux {
groups = "pwm_a_a";
function = "pwm_a";
};
};
pwm_a_x18_pins: pwm_a_x18 {
mux {
groups = "pwm_a_x18";
function = "pwm_a";
};
};
pwm_a_x20_pins: pwm_a_x20 {
mux {
groups = "pwm_a_x20";
function = "pwm_a";
};
};
pwm_a_z_pins: pwm_a_z {
mux {
groups = "pwm_a_z";
function = "pwm_a";
};
};
pwm_b_a_pins: pwm_b_a {
mux {
groups = "pwm_b_a";
function = "pwm_b";
};
};
pwm_b_x_pins: pwm_b_x {
mux {
groups = "pwm_b_x";
function = "pwm_b";
};
};
pwm_b_z_pins: pwm_b_z {
mux {
groups = "pwm_b_z";
function = "pwm_b";
};
};
pwm_c_a_pins: pwm_c_a {
mux {
groups = "pwm_c_a";
function = "pwm_c";
};
};
pwm_c_x10_pins: pwm_c_x10 {
mux {
groups = "pwm_c_x10";
function = "pwm_c";
};
};
pwm_c_x17_pins: pwm_c_x17 {
mux {
groups = "pwm_c_x17";
function = "pwm_c";
};
};
pwm_d_x11_pins: pwm_d_x11 {
mux {
groups = "pwm_d_x11";
function = "pwm_d";
};
};
pwm_d_x16_pins: pwm_d_x16 {
mux {
groups = "pwm_d_x16";
function = "pwm_d";
};
};
};
};
sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>;
@ -182,6 +326,37 @@ aobus: bus@ff800000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-axg-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 15>;
};
};
pwm_AO_ab: pwm@7000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x07000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_AO_cd: pwm@2000 {
compatible = "amlogic,axg-ao-pwm";
reg = <0x0 0x02000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;