mirror of https://gitee.com/openkylin/linux.git
clk: meson: gxbb: Add VPU and VAPB clocks data
The Amlogic Meson GX SoCs needs these two clocks to power up the VPU power domain. These two clocks are similar to the MALI clocks by having a glitch-free mux and two similar clocks with gate, divider and muxes. Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
parent
4cf8f811c6
commit
762a1f2098
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@ -1131,6 +1131,253 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
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},
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};
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/* VPU Clock */
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static u32 mux_table_vpu[] = {0, 1, 2, 3};
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static const char * const gxbb_vpu_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
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};
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static struct clk_mux gxbb_vpu_0_sel = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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.lock = &clk_lock,
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.table = mux_table_vpu,
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_sel",
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.ops = &clk_mux_ops,
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/*
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* bits 9:10 selects from 4 possible parents:
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* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
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*/
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.parent_names = gxbb_vpu_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_divider gxbb_vpu_0_div = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "vpu_0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_vpu_0 = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.bit_idx = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "vpu_0",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "vpu_0_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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static struct clk_mux gxbb_vpu_1_sel = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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.lock = &clk_lock,
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.table = mux_table_vpu,
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_sel",
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.ops = &clk_mux_ops,
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/*
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* bits 25:26 selects from 4 possible parents:
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* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
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*/
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.parent_names = gxbb_vpu_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_divider gxbb_vpu_1_div = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "vpu_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_vpu_1 = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.bit_idx = 24,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "vpu_1",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "vpu_1_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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static struct clk_mux gxbb_vpu = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.mask = 1,
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.shift = 31,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vpu",
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.ops = &clk_mux_ops,
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/*
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* bit 31 selects from 2 possible parents:
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* vpu_0 or vpu_1
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*/
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.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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/* VAPB Clock */
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static u32 mux_table_vapb[] = {0, 1, 2, 3};
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static const char * const gxbb_vapb_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
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};
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static struct clk_mux gxbb_vapb_0_sel = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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.lock = &clk_lock,
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.table = mux_table_vapb,
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.hw.init = &(struct clk_init_data){
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.name = "vapb_0_sel",
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.ops = &clk_mux_ops,
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/*
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* bits 9:10 selects from 4 possible parents:
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* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
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*/
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.parent_names = gxbb_vapb_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_divider gxbb_vapb_0_div = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vapb_0_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "vapb_0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_vapb_0 = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.bit_idx = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "vapb_0",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "vapb_0_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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static struct clk_mux gxbb_vapb_1_sel = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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.lock = &clk_lock,
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.table = mux_table_vapb,
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.hw.init = &(struct clk_init_data){
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.name = "vapb_1_sel",
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.ops = &clk_mux_ops,
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/*
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* bits 25:26 selects from 4 possible parents:
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* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
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*/
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.parent_names = gxbb_vapb_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_divider gxbb_vapb_1_div = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vapb_1_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "vapb_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_vapb_1 = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.bit_idx = 24,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "vapb_1",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "vapb_1_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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static struct clk_mux gxbb_vapb_sel = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.mask = 1,
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.shift = 31,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vapb_sel",
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.ops = &clk_mux_ops,
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/*
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* bit 31 selects from 2 possible parents:
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* vapb_0 or vapb_1
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*/
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.parent_names = (const char *[]){ "vapb_0", "vapb_1" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_gate gxbb_vapb = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.bit_idx = 30,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "vapb",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "vapb_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@ -1349,6 +1596,21 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
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[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
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[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
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[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
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[CLKID_VPU_0] = &gxbb_vpu_0.hw,
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[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
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[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
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[CLKID_VPU_1] = &gxbb_vpu_1.hw,
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[CLKID_VPU] = &gxbb_vpu.hw,
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[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
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[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
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[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
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[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
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[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
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[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
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[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
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[CLKID_VAPB] = &gxbb_vapb.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -1481,6 +1743,21 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
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[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
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[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
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[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
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[CLKID_VPU_0] = &gxbb_vpu_0.hw,
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[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
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[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
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[CLKID_VPU_1] = &gxbb_vpu_1.hw,
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[CLKID_VPU] = &gxbb_vpu.hw,
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[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
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[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
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[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
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[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
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[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
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[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
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[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
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[CLKID_VAPB] = &gxbb_vapb.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -1600,6 +1877,11 @@ static struct clk_gate *const gxbb_clk_gates[] = {
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&gxbb_sd_emmc_a_clk0,
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&gxbb_sd_emmc_b_clk0,
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&gxbb_sd_emmc_c_clk0,
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&gxbb_vpu_0,
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&gxbb_vpu_1,
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&gxbb_vapb_0,
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&gxbb_vapb_1,
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&gxbb_vapb,
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};
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static struct clk_mux *const gxbb_clk_muxes[] = {
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@ -1615,6 +1897,12 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
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&gxbb_sd_emmc_a_clk0_sel,
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&gxbb_sd_emmc_b_clk0_sel,
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&gxbb_sd_emmc_c_clk0_sel,
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&gxbb_vpu_0_sel,
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&gxbb_vpu_1_sel,
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&gxbb_vpu,
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&gxbb_vapb_0_sel,
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&gxbb_vapb_1_sel,
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&gxbb_vapb_sel,
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};
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static struct clk_divider *const gxbb_clk_dividers[] = {
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@ -1627,6 +1915,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
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&gxbb_sd_emmc_a_clk0_div,
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&gxbb_sd_emmc_b_clk0_div,
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&gxbb_sd_emmc_c_clk0_div,
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&gxbb_vpu_0_div,
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&gxbb_vpu_1_div,
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&gxbb_vapb_0_div,
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&gxbb_vapb_1_div,
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};
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static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
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