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usb: xhci-pci: Add support for reset controllers
Some atypical users of xhci-pci might need to manually reset their xHCI controller before starting the HCD setup. Check if a reset controller device is available to the PCI bus and trigger a reset. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20200629161845.6021-6-nsaenzjulienne@suse.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -12,6 +12,7 @@
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <linux/reset.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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@ -346,6 +347,7 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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struct xhci_hcd *xhci;
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struct usb_hcd *hcd;
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struct xhci_driver_data *driver_data;
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struct reset_control *reset;
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driver_data = (struct xhci_driver_data *)id->driver_data;
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if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
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@ -354,6 +356,11 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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return retval;
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}
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reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
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if (IS_ERR(reset))
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return PTR_ERR(reset);
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reset_control_reset(reset);
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/* Prevent runtime suspending between USB-2 and USB-3 initialization */
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pm_runtime_get_noresume(&dev->dev);
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@ -371,6 +378,7 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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/* USB 2.0 roothub is stored in the PCI device now. */
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hcd = dev_get_drvdata(&dev->dev);
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xhci = hcd_to_xhci(hcd);
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xhci->reset = reset;
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xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
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pci_name(dev), hcd);
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if (!xhci->shared_hcd) {
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@ -522,6 +530,8 @@ static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval = 0;
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reset_control_reset(xhci->reset);
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/* The BIOS on systems with the Intel Panther Point chipset may or may
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* not support xHCI natively. That means that during system resume, it
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* may switch the ports back to EHCI so that users can use their
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@ -1770,6 +1770,8 @@ struct xhci_hcd {
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/* optional clocks */
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struct clk *clk;
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struct clk *reg_clk;
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/* optional reset controller */
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struct reset_control *reset;
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/* data structures */
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struct xhci_device_context_array *dcbaa;
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struct xhci_ring *cmd_ring;
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