mirror of https://gitee.com/openkylin/linux.git
ASoC: tegra: call pm_runtime APIs around register accesses
Call pm_runtime_get_sync() before all register accesses; the HW requires clocks to be running when accessing registers. This hasn't been needed to date, since all register IO was performed while playback was active, and hence the ASoC core had already called pm_runtime_get(). However, an imminent future commit will allocate and set up the FIFOs and routing during probe(), when that "protection" won't be in place. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
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@ -114,6 +114,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
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(channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
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*reqsel = ahub->dma_sel + channel;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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@ -140,6 +142,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
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(channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
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ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
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@ -149,12 +153,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg, val;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
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tegra30_apbif_write(reg, val);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
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@ -164,12 +172,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg, val;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
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tegra30_apbif_write(reg, val);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
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@ -204,6 +216,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
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(channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
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*reqsel = ahub->dma_sel + channel;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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@ -230,6 +244,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
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(channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
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ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
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@ -239,12 +255,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
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int reg, val;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
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tegra30_apbif_write(reg, val);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
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@ -254,12 +274,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
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int reg, val;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_CHANNEL_CTRL +
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
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val = tegra30_apbif_read(reg);
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
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tegra30_apbif_write(reg, val);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
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@ -280,10 +304,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_AUDIO_RX +
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
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tegra30_audio_write(reg, 1 << txcif);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
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@ -293,10 +321,14 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
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int reg;
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pm_runtime_get_sync(ahub->dev);
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reg = TEGRA30_AHUB_AUDIO_RX +
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
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tegra30_audio_write(reg, 0);
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pm_runtime_put(ahub->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
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