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arm64: dts: renesas: r8a77961: Add PCIe device nodes 

Add PCIe device nodes for r8a77961 (R-Car M3-W+).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1586515634-28095-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda 2020-04-10 19:47:14 +09:00 committed by Geert Uytterhoeven
parent 174d0967b3
commit 76e6c82c53
1 changed files with 46 additions and 2 deletions
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48
arch/arm64/boot/dts/renesas/r8a77961.dtsi
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@ -1323,13 +1323,57 @@ gic: interrupt-controller@f1010000 {
};
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a77961",
"renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
/* placeholder */
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 319>;
status = "disabled";
};
pciec1: pcie@ee800000 {
compatible = "renesas,pcie-r8a77961",
"renesas,pcie-rcar-gen3";
reg = <0 0xee800000 0 0x80000>;
/* placeholder */
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 318>;
status = "disabled";
};
csi20: csi2@fea80000 {