mirror of https://gitee.com/openkylin/linux.git
drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
The MIPI clock calculations for the addtional clock are revised from B0 stepping onwards, the bit definitions have changed compared to old stepping. v2: Fixing compilation warning. v3: Retained the old Macros (Jani) Signed-off-by: Deepak M <m.deepak@intel.com> Tested-by: Ramalingam C <ramalingam.c@intel.com> # BXT-T with Tianma panel Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455556437-29267-1-git-send-email-m.deepak@intel.com
This commit is contained in:
Deepak M
Jani Nikula
parent
e3bddded40
commit
782d25cac6
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@ -7669,58 +7669,62 @@ enum skl_disp_power_wells {
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#define BXT_MIPI_DIV_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
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BXT_MIPI2_DIV_SHIFT)
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/* Var clock divider to generate TX source. Result must be < 39.5 M */
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#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
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#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
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#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
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_MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
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BXT_MIPI2_ESCLK_VAR_DIV_MASK)
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#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
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(val << BXT_MIPI_DIV_SHIFT(port))
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/* TX control divider to select actual TX clock output from (8x/var) */
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#define BXT_MIPI1_TX_ESCLK_SHIFT 21
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#define BXT_MIPI2_TX_ESCLK_SHIFT 5
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#define BXT_MIPI1_TX_ESCLK_SHIFT 26
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#define BXT_MIPI2_TX_ESCLK_SHIFT 10
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#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
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BXT_MIPI2_TX_ESCLK_SHIFT)
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#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
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#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
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#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
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#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
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#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
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_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
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BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
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#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
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(0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
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#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
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(0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
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#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
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(0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
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/* RX control divider to select actual RX clock output from 8x*/
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#define BXT_MIPI1_RX_ESCLK_SHIFT 19
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#define BXT_MIPI2_RX_ESCLK_SHIFT 3
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#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
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BXT_MIPI2_RX_ESCLK_SHIFT)
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#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
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#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
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#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
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(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
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#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
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(1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
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#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
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(2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
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#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
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(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
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/* BXT-A WA: Always prog DPHY dividers to 00 */
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#define BXT_MIPI1_DPHY_DIV_SHIFT 16
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#define BXT_MIPI2_DPHY_DIV_SHIFT 0
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#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
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BXT_MIPI2_DPHY_DIV_SHIFT)
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#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
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#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
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#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
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(3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
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BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
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#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
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((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
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/* RX upper control divider to select actual RX clock output from 8x */
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#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
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#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
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#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
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BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
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#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
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#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
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#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
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BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
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#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
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((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
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/* 8/3X divider to select the actual 8/3X clock output from 8x */
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#define BXT_MIPI1_8X_BY3_SHIFT 19
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#define BXT_MIPI2_8X_BY3_SHIFT 3
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#define BXT_MIPI_8X_BY3_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
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BXT_MIPI2_8X_BY3_SHIFT)
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#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
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#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
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#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
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_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
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BXT_MIPI2_8X_BY3_DIVIDER_MASK)
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#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
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((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
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/* RX lower control divider to select actual RX clock output from 8x */
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#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
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#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
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#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
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BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
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#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
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#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
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#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
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BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
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#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
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((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
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#define RX_DIVIDER_BIT_1_2 0x3
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#define RX_DIVIDER_BIT_3_4 0xC
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/* BXT MIPI mode configure */
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#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
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@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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/* Program BXT Mipi clocks and dividers */
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static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
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{
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u32 tmp;
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u32 divider;
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u32 dsi_rate;
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u32 pll_ratio;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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u32 dsi_rate = 0;
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u32 pll_ratio = 0;
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u32 rx_div;
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u32 tx_div;
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u32 rx_div_upper;
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u32 rx_div_lower;
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u32 mipi_8by3_divider;
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/* Clear old configurations */
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tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
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tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
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tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
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/* Get the current DSI rate(actual) */
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pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
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BXT_DSI_PLL_RATIO_MASK;
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dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
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/* Max possible output of clock is 39.5 MHz, program value -1 */
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divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
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tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
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/*
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* tx clock should be <= 20MHz and the div value must be
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* subtracted by 1 as per bspec
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*/
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tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
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/*
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* rx clock should be <= 150MHz and the div value must be
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* subtracted by 1 as per bspec
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*/
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rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
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/*
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* Tx escape clock must be as close to 20MHz possible, but should
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* not exceed it. Hence select divide by 2
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* rx divider value needs to be updated in the
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* two differnt bit fields in the register hence splitting the
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* rx divider value accordingly
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*/
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tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
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rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
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rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
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tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
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/* As per bpsec program the 8/3X clock divider to the below value */
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if (dev_priv->vbt.dsi.config->is_cmd_mode)
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mipi_8by3_divider = 0x2;
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else
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mipi_8by3_divider = 0x3;
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tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
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tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
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tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
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tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
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I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
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}
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@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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/* Clear old configurations */
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tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
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tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
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tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
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I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
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I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
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}
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