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x86, mce: enable MCE_INTEL for 32bit new MCE 

Enable the 64bit MCE_INTEL code (CMCI, thermal interrupts) for 32bit NEW_MCE.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Andi Kleen 2009-04-28 23:32:56 +02:00 committed by H. Peter Anvin
parent 45f458e9a8
commit 7856f6cce4
8 changed files with 16 additions and 7 deletions
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2
arch/x86/Kconfig
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@ -808,7 +808,7 @@ config X86_NEW_MCE
config X86_MCE_INTEL config X86_MCE_INTEL
def_bool y def_bool y
prompt "Intel MCE features" prompt "Intel MCE features"
depends on X86_64 && X86_MCE && X86_LOCAL_APIC depends on X86_NEW_MCE && X86_LOCAL_APIC
---help--- ---help---
Additional support for intel specific MCE features such as Additional support for intel specific MCE features such as
the thermal monitor. the thermal monitor.

4
arch/x86/include/asm/entry_arch.h
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@ -56,4 +56,8 @@ BUILD_INTERRUPT(perf_counter_interrupt, LOCAL_PERF_VECTOR)
BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR) BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
#endif #endif
#ifdef CONFIG_X86_MCE_THRESHOLD
BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
#endif
#endif #endif

2
arch/x86/include/asm/hardirq.h
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@ -20,7 +20,7 @@ typedef struct {
#endif #endif
#ifdef CONFIG_X86_MCE #ifdef CONFIG_X86_MCE
unsigned int irq_thermal_count; unsigned int irq_thermal_count;
# ifdef CONFIG_X86_64 # ifdef CONFIG_X86_MCE_THRESHOLD
unsigned int irq_threshold_count; unsigned int irq_threshold_count;
# endif # endif
#endif #endif

5
arch/x86/include/asm/irq_vectors.h
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@ -87,10 +87,11 @@
#define CALL_FUNCTION_SINGLE_VECTOR 0xfb #define CALL_FUNCTION_SINGLE_VECTOR 0xfb
#define THERMAL_APIC_VECTOR 0xfa #define THERMAL_APIC_VECTOR 0xfa
#define THRESHOLD_APIC_VECTOR 0xf9
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
/* 0xf8 - 0xf9 : free */ /* 0xf9 : free */
#else #else
# define THRESHOLD_APIC_VECTOR 0xf9
# define UV_BAU_MESSAGE 0xf8 # define UV_BAU_MESSAGE 0xf8
#endif #endif

2
arch/x86/kernel/cpu/mcheck/threshold.c
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@ -17,7 +17,7 @@ static void default_threshold_interrupt(void)
void (*mce_threshold_vector)(void) = default_threshold_interrupt; void (*mce_threshold_vector)(void) = default_threshold_interrupt;
asmlinkage void mce_threshold_interrupt(void) asmlinkage void smp_threshold_interrupt(void)
{ {
exit_idle(); exit_idle();
irq_enter(); irq_enter();

2
arch/x86/kernel/entry_64.S
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@ -1007,7 +1007,7 @@ apicinterrupt INVALIDATE_TLB_VECTOR_START+7 \
#endif #endif
apicinterrupt THRESHOLD_APIC_VECTOR \ apicinterrupt THRESHOLD_APIC_VECTOR \
threshold_interrupt mce_threshold_interrupt threshold_interrupt smp_threshold_interrupt
apicinterrupt THERMAL_APIC_VECTOR \ apicinterrupt THERMAL_APIC_VECTOR \
thermal_interrupt smp_thermal_interrupt thermal_interrupt smp_thermal_interrupt

4
arch/x86/kernel/irqinit_32.c
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@ -186,6 +186,10 @@ void __init native_init_IRQ(void)
alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
#endif #endif
#ifdef CONFIG_X86_MCE_THRESHOLD
alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
#endif
if (!acpi_ioapic) if (!acpi_ioapic)
setup_irq(2, &irq2); setup_irq(2, &irq2);

2
arch/x86/kernel/traps.c
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@ -804,7 +804,7 @@ asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
{ {
} }
asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void) asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
{ {
} }