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drm/amdgpu:fix gmc_v9 vm fault process for SRIOV 

for SRIOV we cannot use access register when in IRQ routine
with regular KIQ method

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2017-03-22 18:01:59 +08:00 committed by Alex Deucher
parent 6e9dc86121
commit 79a0c4655e
1 changed files with 16 additions and 8 deletions
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24
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
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@ -137,20 +137,28 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
addr = (u64)entry->src_data[0] << 12; addr = (u64)entry->src_data[0] << 12;
addr |= ((u64)entry->src_data[1] & 0xf) << 44; addr |= ((u64)entry->src_data[1] & 0xf) << 44;
if (entry->vm_id_src) { if (!amdgpu_sriov_vf(adev)) {
status = RREG32(mmhub->vm_l2_pro_fault_status); if (entry->vm_id_src) {
WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1); status = RREG32(mmhub->vm_l2_pro_fault_status);
} else { WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1);
status = RREG32(gfxhub->vm_l2_pro_fault_status); } else {
WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1); status = RREG32(gfxhub->vm_l2_pro_fault_status);
} WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1);
}
DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) " DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) "
"at page 0x%016llx from %d\n" "at page 0x%016llx from %d\n"
"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
entry->vm_id_src ? "mmhub" : "gfxhub", entry->vm_id_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id, entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id,
addr, entry->client_id, status); addr, entry->client_id, status);
} else {
DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) "
"at page 0x%016llx from %d\n",
entry->vm_id_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id,
addr, entry->client_id);
}
return 0; return 0;
} }