mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: hook navi10 pplib functions
during bring up time, before window dc-ppplib interface design, linux dc use raven dc-pplib interface. now nvai10 dc-pplib-smu interface is changed and verified under window, navi10 need its specific dc-pplib-smu interface. todo: hook set_hard_min_uclk_by_freq, get_maximum_sustainable_clocks Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
hersen wu
Alex Deucher
parent
be9a7355e9
commit
79a7b060d8
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@ -647,16 +647,279 @@ void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
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pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
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pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
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}
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}
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enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
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wm_with_clock_ranges.wm_dmif_clocks_ranges;
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struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
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wm_with_clock_ranges.wm_mcif_clocks_ranges;
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int32_t i;
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wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
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wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
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for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
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if (ranges->reader_wm_sets[i].wm_inst > 3)
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wm_dce_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_dce_clocks[i].wm_set_id =
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ranges->reader_wm_sets[i].wm_inst;
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wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
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wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
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wm_dce_clocks[i].wm_max_mem_clk_in_khz =
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ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
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wm_dce_clocks[i].wm_min_mem_clk_in_khz =
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ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
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}
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for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
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if (ranges->writer_wm_sets[i].wm_inst > 3)
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wm_soc_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_soc_clocks[i].wm_set_id =
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ranges->writer_wm_sets[i].wm_inst;
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wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
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wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
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wm_soc_clocks[i].wm_max_mem_clk_in_khz =
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ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
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wm_soc_clocks[i].wm_min_mem_clk_in_khz =
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ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
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}
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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/* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
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* 1: fail
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*/
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if (smu_set_watermarks_for_clock_ranges(&adev->smu,
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&wm_with_clock_ranges))
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return PP_SMU_RESULT_UNSUPPORTED;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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/* 0: successful or smu.funcs->set_azalia_d3_pme = NULL; 1: fail */
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if (smu_set_azalia_d3_pme(smu))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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/* 0: successful or smu.funcs->set_display_count = NULL; 1: fail */
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if (smu_set_display_count(smu, count))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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/* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */
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if (smu_set_deep_sleep_dcefclk(smu, mhz))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
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struct pp_smu *pp, int mhz)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct pp_display_clock_request clock_req;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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clock_req.clock_type = amd_pp_dcef_clock;
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clock_req.clock_freq_in_khz = mhz * 1000;
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/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
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* 1: fail
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*/
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if (smu_display_clock_voltage_request(smu, &clock_req))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct pp_display_clock_request clock_req;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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clock_req.clock_type = amd_pp_mem_clock;
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clock_req.clock_freq_in_khz = mhz * 1000;
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/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
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* 1: fail
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*/
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if (smu_display_clock_voltage_request(smu, &clock_req))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
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enum pp_smu_nv_clock_id clock_id, int mhz)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct pp_display_clock_request clock_req;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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switch (clock_id) {
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case PP_SMU_NV_DISPCLK:
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clock_req.clock_type = amd_pp_disp_clock;
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break;
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case PP_SMU_NV_PHYCLK:
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clock_req.clock_type = amd_pp_phy_clock;
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break;
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case PP_SMU_NV_PIXELCLK:
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clock_req.clock_type = amd_pp_pixel_clock;
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break;
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default:
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break;
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}
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clock_req.clock_freq_in_khz = mhz * 1000;
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/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
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* 1: fail
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*/
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if (smu_display_clock_voltage_request(smu, &clock_req))
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return PP_SMU_RESULT_FAIL;
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return PP_SMU_RESULT_OK;
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}
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enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
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struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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if (!smu->funcs->get_max_sustainable_clocks_by_dc)
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return PP_SMU_RESULT_UNSUPPORTED;
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if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
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return PP_SMU_RESULT_OK;
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return PP_SMU_RESULT_FAIL;
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}
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enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
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unsigned int *clock_values_in_khz, unsigned int *num_states)
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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if (!smu->ppt_funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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if (!smu->ppt_funcs->get_uclk_dpm_states)
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return PP_SMU_RESULT_UNSUPPORTED;
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if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
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clock_values_in_khz, num_states))
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return PP_SMU_RESULT_OK;
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return PP_SMU_RESULT_FAIL;
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}
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void dm_pp_get_funcs(
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void dm_pp_get_funcs(
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struct dc_context *ctx,
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struct dc_context *ctx,
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struct pp_smu_funcs *funcs)
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struct pp_smu_funcs *funcs)
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{
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{
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funcs->rv_funcs.pp_smu.dm = ctx;
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switch (ctx->dce_version) {
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funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
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case DCN_VERSION_1_0:
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funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
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case DCN_VERSION_1_01:
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funcs->rv_funcs.set_display_count = pp_rv_set_active_display_count;
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funcs->ctx.ver = PP_SMU_VER_RV;
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funcs->rv_funcs.set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk;
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funcs->rv_funcs.pp_smu.dm = ctx;
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funcs->rv_funcs.set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq;
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funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
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funcs->rv_funcs.set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq;
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funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
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}
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funcs->rv_funcs.set_display_count =
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pp_rv_set_active_display_count;
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funcs->rv_funcs.set_min_deep_sleep_dcfclk =
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pp_rv_set_min_deep_sleep_dcfclk;
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funcs->rv_funcs.set_hard_min_dcfclk_by_freq =
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pp_rv_set_hard_min_dcefclk_by_freq;
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funcs->rv_funcs.set_hard_min_fclk_by_freq =
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pp_rv_set_hard_min_fclk_by_freq;
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break;
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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case DCN_VERSION_2_0:
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funcs->ctx.ver = PP_SMU_VER_NV;
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funcs->nv_funcs.pp_smu.dm = ctx;
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funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
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funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
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pp_nv_set_hard_min_dcefclk_by_freq;
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funcs->nv_funcs.set_min_deep_sleep_dcfclk =
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pp_nv_set_min_deep_sleep_dcfclk;
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funcs->nv_funcs.set_voltage_by_freq =
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pp_nv_set_voltage_by_freq;
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funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
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/* todo set_pme_wa_enable cause 4k@6ohz display not light up */
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funcs->nv_funcs.set_pme_wa_enable = NULL;
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/* todo debug waring message */
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funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL;
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/* todo compare data with window driver*/
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funcs->nv_funcs.get_maximum_sustainable_clocks = NULL;
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/*todo compare data with window driver */
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funcs->nv_funcs.get_uclk_dpm_states = NULL;
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break;
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#endif
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default:
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DRM_ERROR("smu version is not supported !\n");
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break;
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}
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}
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