mirror of https://gitee.com/openkylin/linux.git
iwlwifi: dbg: dump data according to the new ini TLVs
When ini TLVs are loaded, dump data according to the stored configuration. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
09b0b99007
commit
7a14c23dcd
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@ -605,6 +605,28 @@ static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
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IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
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}
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static void iwl_fw_dump_named_mem(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_error_dump_data **dump_data,
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u32 len, u32 ofs, u8 *name, u8 name_len)
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{
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struct iwl_fw_error_dump_named_mem *dump_mem;
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if (!len)
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return;
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(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
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(*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
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dump_mem = (void *)(*dump_data)->data;
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dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_NAMED_MEM);
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dump_mem->offset = cpu_to_le32(ofs);
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dump_mem->name_len = name_len;
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memcpy(dump_mem->name, name, name_len);
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iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
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*dump_data = iwl_fw_error_next_data(*dump_data);
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IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
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}
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#define ADD_LEN(len, item_len, const_len) \
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do {size_t item = item_len; len += (!!item) * const_len + item; } \
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while (0)
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@ -928,6 +950,238 @@ _iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
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return dump_file;
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}
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static void iwl_dump_prph_ini(struct iwl_trans *trans,
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struct iwl_fw_error_dump_data **data,
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struct iwl_fw_ini_region_cfg *reg)
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{
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struct iwl_fw_error_dump_prph *prph;
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unsigned long flags;
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u32 i, size = le32_to_cpu(reg->num_regions);
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IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
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if (!iwl_trans_grab_nic_access(trans, &flags))
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return;
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for (i = 0; i < size; i++) {
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(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
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(*data)->len = cpu_to_le32(le32_to_cpu(reg->size) +
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sizeof(*prph));
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prph = (void *)(*data)->data;
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prph->prph_start = reg->start_addr[i];
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prph->data[0] = cpu_to_le32(iwl_read_prph_no_grab(trans,
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le32_to_cpu(prph->prph_start)));
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*data = iwl_fw_error_next_data(*data);
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}
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iwl_trans_release_nic_access(trans, &flags);
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}
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static void iwl_dump_csr_ini(struct iwl_trans *trans,
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struct iwl_fw_error_dump_data **data,
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struct iwl_fw_ini_region_cfg *reg)
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{
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int i, num = le32_to_cpu(reg->num_regions);
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u32 size = le32_to_cpu(reg->size);
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IWL_DEBUG_INFO(trans, "WRT CSR dump\n");
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for (i = 0; i < num; i++) {
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u32 add = le32_to_cpu(reg->start_addr[i]);
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__le32 *val;
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int j;
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(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
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(*data)->len = cpu_to_le32(size);
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val = (void *)(*data)->data;
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for (j = 0; j < size; j += 4)
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*val++ = cpu_to_le32(iwl_trans_read32(trans, j + add));
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*data = iwl_fw_error_next_data(*data);
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}
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}
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static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_ini_trigger *trigger)
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{
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int i, num, size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data);
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if (!trigger || !trigger->num_regions)
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return 0;
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num = le32_to_cpu(trigger->num_regions);
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for (i = 0; i < num; i++) {
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u32 reg_id = le32_to_cpu(trigger->data[i]);
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struct iwl_fw_ini_region_cfg *reg;
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enum iwl_fw_ini_region_type type;
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u32 num_entries;
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if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)))
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continue;
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reg = fwrt->dump.active_regs[reg_id].reg;
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if (WARN(!reg, "Unassigned region %d\n", reg_id))
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continue;
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type = le32_to_cpu(reg->region_type);
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num_entries = le32_to_cpu(reg->num_regions);
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switch (type) {
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case IWL_FW_INI_REGION_DEVICE_MEMORY:
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size += hdr_len +
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sizeof(struct iwl_fw_error_dump_named_mem) +
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le32_to_cpu(reg->size);
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break;
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case IWL_FW_INI_REGION_PERIPHERY_MAC:
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case IWL_FW_INI_REGION_PERIPHERY_PHY:
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case IWL_FW_INI_REGION_PERIPHERY_AUX:
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size += num_entries *
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(hdr_len +
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sizeof(struct iwl_fw_error_dump_prph) +
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sizeof(u32));
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break;
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case IWL_FW_INI_REGION_TXF:
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size += iwl_fw_txf_len(fwrt, &fwrt->smem_cfg);
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break;
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case IWL_FW_INI_REGION_RXF:
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size += iwl_fw_rxf_len(fwrt, &fwrt->smem_cfg);
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break;
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case IWL_FW_INI_REGION_PAGING:
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if (!iwl_fw_dbg_is_paging_enabled(fwrt))
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break;
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size += fwrt->num_of_paging_blk *
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(hdr_len +
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sizeof(struct iwl_fw_error_dump_paging) +
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PAGING_BLOCK_SIZE);
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break;
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case IWL_FW_INI_REGION_CSR:
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size += num_entries *
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(hdr_len + le32_to_cpu(reg->size));
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break;
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case IWL_FW_INI_REGION_DRAM_BUFFER:
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/* Transport takes care of DRAM dumping */
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case IWL_FW_INI_REGION_INTERNAL_BUFFER:
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case IWL_FW_INI_REGION_DRAM_IMR:
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/* Undefined yet */
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default:
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break;
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}
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}
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return size;
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}
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static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_ini_trigger *trigger,
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struct iwl_fw_error_dump_data **data,
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u32 *dump_mask)
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{
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int i, num = le32_to_cpu(trigger->num_regions);
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for (i = 0; i < num; i++) {
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u32 reg_id = le32_to_cpu(trigger->data[i]);
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enum iwl_fw_ini_region_type type;
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struct iwl_fw_ini_region_cfg *reg;
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if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))
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continue;
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reg = fwrt->dump.active_regs[reg_id].reg;
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/* Don't warn, get_trigger_len already warned */
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if (!reg)
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continue;
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type = le32_to_cpu(reg->region_type);
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switch (type) {
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case IWL_FW_INI_REGION_DEVICE_MEMORY:
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if (WARN_ON(le32_to_cpu(reg->num_regions) > 1))
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continue;
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iwl_fw_dump_named_mem(fwrt, data,
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le32_to_cpu(reg->size),
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le32_to_cpu(reg->start_addr[0]),
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reg->name,
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le32_to_cpu(reg->name_len));
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break;
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case IWL_FW_INI_REGION_PERIPHERY_MAC:
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case IWL_FW_INI_REGION_PERIPHERY_PHY:
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case IWL_FW_INI_REGION_PERIPHERY_AUX:
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iwl_dump_prph_ini(fwrt->trans, data, reg);
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break;
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case IWL_FW_INI_REGION_DRAM_BUFFER:
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*dump_mask |= IWL_FW_ERROR_DUMP_FW_MONITOR;
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break;
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case IWL_FW_INI_REGION_PAGING:
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if (iwl_fw_dbg_is_paging_enabled(fwrt))
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iwl_dump_paging(fwrt, data);
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else
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*dump_mask |= IWL_FW_ERROR_DUMP_PAGING;
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break;
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case IWL_FW_INI_REGION_TXF:
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iwl_fw_dump_txf(fwrt, data);
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break;
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case IWL_FW_INI_REGION_RXF:
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iwl_fw_dump_rxf(fwrt, data);
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break;
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case IWL_FW_INI_REGION_CSR:
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iwl_dump_csr_ini(fwrt->trans, data, reg);
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break;
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case IWL_FW_INI_REGION_DRAM_IMR:
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case IWL_FW_INI_REGION_INTERNAL_BUFFER:
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/* This is undefined yet */
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default:
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break;
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}
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}
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}
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static struct iwl_fw_error_dump_file *
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_iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_dump_ptrs *fw_error_dump,
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u32 *dump_mask)
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{
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int size, id = le32_to_cpu(fwrt->dump.desc->trig_desc.type);
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struct iwl_fw_error_dump_data *dump_data;
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struct iwl_fw_error_dump_file *dump_file;
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struct iwl_fw_ini_trigger *trigger, *ext;
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if (id == FW_DBG_TRIGGER_FW_ASSERT)
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id = IWL_FW_TRIGGER_ID_FW_ASSERT;
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else if (id == FW_DBG_TRIGGER_USER)
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id = IWL_FW_TRIGGER_ID_USER_TRIGGER;
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else if (id < FW_DBG_TRIGGER_MAX)
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return NULL;
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if (WARN_ON(id >= ARRAY_SIZE(fwrt->dump.active_trigs)))
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return NULL;
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trigger = fwrt->dump.active_trigs[id].conf;
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ext = fwrt->dump.active_trigs[id].conf_ext;
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size = sizeof(*dump_file);
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size += iwl_fw_ini_get_trigger_len(fwrt, trigger);
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size += iwl_fw_ini_get_trigger_len(fwrt, ext);
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if (!size)
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return NULL;
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dump_file = vzalloc(size);
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if (!dump_file)
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return NULL;
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fw_error_dump->fwrt_ptr = dump_file;
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dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
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dump_data = (void *)dump_file->data;
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dump_file->file_len = cpu_to_le32(size);
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*dump_mask = 0;
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if (trigger)
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iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data, dump_mask);
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if (ext)
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iwl_fw_ini_dump_trigger(fwrt, ext, &dump_data, dump_mask);
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return dump_file;
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}
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void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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{
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struct iwl_fw_dump_ptrs *fw_error_dump;
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@ -948,13 +1202,18 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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if (!fw_error_dump)
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goto out;
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dump_file = _iwl_fw_error_dump(fwrt, fw_error_dump);
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if (fwrt->trans->ini_valid)
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dump_file = _iwl_fw_error_ini_dump(fwrt, fw_error_dump,
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&dump_mask);
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else
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dump_file = _iwl_fw_error_dump(fwrt, fw_error_dump);
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if (!dump_file) {
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kfree(fw_error_dump);
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goto out;
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}
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if (fwrt->dump.monitor_only)
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if (!fwrt->trans->ini_valid && fwrt->dump.monitor_only)
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dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR;
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fw_error_dump->trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask);
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@ -329,7 +329,7 @@ void iwl_fw_error_dump_wk(struct work_struct *work);
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static inline bool iwl_fw_dbg_type_on(struct iwl_fw_runtime *fwrt, u32 type)
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{
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return (fwrt->fw->dbg.dump_mask & BIT(type));
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return (fwrt->fw->dbg.dump_mask & BIT(type) || fwrt->trans->ini_valid);
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}
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static inline bool iwl_fw_dbg_is_d3_debug_enabled(struct iwl_fw_runtime *fwrt)
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@ -249,6 +249,7 @@ struct iwl_fw_error_dump_prph {
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enum iwl_fw_error_dump_mem_type {
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IWL_FW_ERROR_DUMP_MEM_SRAM,
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IWL_FW_ERROR_DUMP_MEM_SMEM,
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IWL_FW_ERROR_DUMP_MEM_NAMED_MEM = 10,
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};
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/**
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@ -263,6 +264,22 @@ struct iwl_fw_error_dump_mem {
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u8 data[];
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};
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/**
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* struct iwl_fw_error_dump_named_mem - chunk of memory
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* @type: &enum iwl_fw_error_dump_mem_type
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* @offset: the offset from which the memory was read
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* @name_len: name length
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* @name: file name
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* @data: the content of the memory
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*/
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struct iwl_fw_error_dump_named_mem {
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__le32 type;
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__le32 offset;
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u8 name_len;
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u8 name[32];
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u8 data[];
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};
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/**
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* struct iwl_fw_error_dump_rb - content of an Receive Buffer
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* @index: the index of the Receive Buffer in the Rx queue
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@ -362,6 +362,12 @@
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#define MON_BUFF_END_ADDR (0xa03c40)
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#define MON_BUFF_WRPTR (0xa03c44)
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#define MON_BUFF_CYCLE_CNT (0xa03c48)
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/* FW monitor family 8000 and on */
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#define MON_BUFF_BASE_ADDR_VER2 (0xa03c3c)
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#define MON_BUFF_END_ADDR_VER2 (0xa03c20)
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#define MON_BUFF_WRPTR_VER2 (0xa03c24)
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#define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)
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#define MON_BUFF_SHIFT_VER2 (0x8)
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#define MON_DMARB_RD_CTL_ADDR (0xa03c60)
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#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
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@ -1050,11 +1050,13 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
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if (ret)
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IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
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mvm->fwrt.dump.conf = FW_DBG_INVALID;
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/* if we have a destination, assume EARLY START */
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if (mvm->fw->dbg.dest_tlv)
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mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
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iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
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if (!mvm->trans->ini_valid) {
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mvm->fwrt.dump.conf = FW_DBG_INVALID;
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/* if we have a destination, assume EARLY START */
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if (mvm->fw->dbg.dest_tlv)
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mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
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iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
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}
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ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
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if (ret)
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@ -94,11 +94,14 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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cpu_to_le64(trans_pcie->rxq->bd_dma);
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/* Configure debug, for integration */
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iwl_pcie_alloc_fw_monitor(trans, 0);
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prph_sc_ctrl->hwm_cfg.hwm_base_addr =
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cpu_to_le64(trans->fw_mon[0].physical);
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prph_sc_ctrl->hwm_cfg.hwm_size =
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cpu_to_le32(trans->fw_mon[0].size);
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if (!trans->ini_valid)
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iwl_pcie_alloc_fw_monitor(trans, 0);
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if (trans->num_blocks) {
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prph_sc_ctrl->hwm_cfg.hwm_base_addr =
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cpu_to_le64(trans->fw_mon[0].physical);
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prph_sc_ctrl->hwm_cfg.hwm_size =
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cpu_to_le32(trans->fw_mon[0].size);
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}
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
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@ -227,7 +227,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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iwl_enable_interrupts(trans);
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/* Configure debug, if exists */
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if (trans->dbg_dest_tlv)
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if (iwl_pcie_dbg_on(trans))
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iwl_pcie_apply_destination(trans);
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/* kick FW self load */
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@ -1009,6 +1009,11 @@ static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
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__iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
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}
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static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
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{
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return (trans->dbg_dest_tlv || trans->ini_valid);
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}
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void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
|
||||
void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
|
||||
|
||||
|
|
|
@ -924,6 +924,20 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)
|
|||
const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
|
||||
int i;
|
||||
|
||||
if (trans->ini_valid) {
|
||||
if (!trans->num_blocks)
|
||||
return;
|
||||
|
||||
iwl_write_prph(trans, MON_BUFF_BASE_ADDR_VER2,
|
||||
trans->fw_mon[0].physical >>
|
||||
MON_BUFF_SHIFT_VER2);
|
||||
iwl_write_prph(trans, MON_BUFF_END_ADDR_VER2,
|
||||
(trans->fw_mon[0].physical +
|
||||
trans->fw_mon[0].size - 256) >>
|
||||
MON_BUFF_SHIFT_VER2);
|
||||
return;
|
||||
}
|
||||
|
||||
IWL_INFO(trans, "Applying debug destination %s\n",
|
||||
get_fw_dbg_mode_string(dest->monitor_mode));
|
||||
|
||||
|
@ -1026,7 +1040,7 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
|
|||
(trans->fw_mon[0].physical +
|
||||
trans->fw_mon[0].size) >> 4);
|
||||
}
|
||||
} else if (trans->dbg_dest_tlv) {
|
||||
} else if (iwl_pcie_dbg_on(trans)) {
|
||||
iwl_pcie_apply_destination(trans);
|
||||
}
|
||||
|
||||
|
@ -1047,7 +1061,7 @@ static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
|
|||
IWL_DEBUG_FW(trans, "working with %s CPU\n",
|
||||
image->is_dual_cpus ? "Dual" : "Single");
|
||||
|
||||
if (trans->dbg_dest_tlv)
|
||||
if (iwl_pcie_dbg_on(trans))
|
||||
iwl_pcie_apply_destination(trans);
|
||||
|
||||
IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
|
||||
|
@ -3015,6 +3029,34 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
|
|||
return monitor_len;
|
||||
}
|
||||
|
||||
static void
|
||||
iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
|
||||
struct iwl_fw_error_dump_fw_mon *fw_mon_data)
|
||||
{
|
||||
u32 base, write_ptr, wrap_cnt;
|
||||
|
||||
/* If there was a dest TLV - use the values from there */
|
||||
if (trans->ini_valid) {
|
||||
base = MON_BUFF_BASE_ADDR_VER2;
|
||||
write_ptr = MON_BUFF_WRPTR_VER2;
|
||||
wrap_cnt = MON_BUFF_CYCLE_CNT_VER2;
|
||||
} else if (trans->dbg_dest_tlv) {
|
||||
write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
|
||||
wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
|
||||
base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
|
||||
} else {
|
||||
base = MON_BUFF_BASE_ADDR;
|
||||
write_ptr = MON_BUFF_WRPTR;
|
||||
wrap_cnt = MON_BUFF_CYCLE_CNT;
|
||||
}
|
||||
fw_mon_data->fw_mon_wr_ptr =
|
||||
cpu_to_le32(iwl_read_prph(trans, write_ptr));
|
||||
fw_mon_data->fw_mon_cycle_cnt =
|
||||
cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
|
||||
fw_mon_data->fw_mon_base_ptr =
|
||||
cpu_to_le32(iwl_read_prph(trans, base));
|
||||
}
|
||||
|
||||
static u32
|
||||
iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
|
||||
struct iwl_fw_error_dump_data **data,
|
||||
|
@ -3024,30 +3066,14 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
|
|||
|
||||
if ((trans->num_blocks &&
|
||||
trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
|
||||
trans->dbg_dest_tlv) {
|
||||
(trans->dbg_dest_tlv && !trans->ini_valid) ||
|
||||
(trans->ini_valid && trans->num_blocks)) {
|
||||
struct iwl_fw_error_dump_fw_mon *fw_mon_data;
|
||||
u32 base, write_ptr, wrap_cnt;
|
||||
|
||||
/* If there was a dest TLV - use the values from there */
|
||||
if (trans->dbg_dest_tlv) {
|
||||
write_ptr =
|
||||
le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
|
||||
wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
|
||||
base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
|
||||
} else {
|
||||
base = MON_BUFF_BASE_ADDR;
|
||||
write_ptr = MON_BUFF_WRPTR;
|
||||
wrap_cnt = MON_BUFF_CYCLE_CNT;
|
||||
}
|
||||
|
||||
(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
|
||||
fw_mon_data = (void *)(*data)->data;
|
||||
fw_mon_data->fw_mon_wr_ptr =
|
||||
cpu_to_le32(iwl_read_prph(trans, write_ptr));
|
||||
fw_mon_data->fw_mon_cycle_cnt =
|
||||
cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
|
||||
fw_mon_data->fw_mon_base_ptr =
|
||||
cpu_to_le32(iwl_read_prph(trans, base));
|
||||
|
||||
iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
|
||||
|
||||
len += sizeof(**data) + sizeof(*fw_mon_data);
|
||||
if (trans->num_blocks) {
|
||||
|
@ -3057,6 +3083,7 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
|
|||
|
||||
monitor_len = trans->fw_mon[0].size;
|
||||
} else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
|
||||
u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
|
||||
/*
|
||||
* Update pointers to reflect actual values after
|
||||
* shifting
|
||||
|
|
Loading…
Reference in New Issue