ARM: DRA7: hwmod: Add data for RNG IP

DRA7 SoC contains hardware random number generator. Add hwmod data for
this IP so that it can be utilized.

Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: squashed the RNG hwmod IP flag fixes from Lokesh,
                  squashed the HS chip fix from Daniel Allred]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Joel Fernandes 2016-10-18 10:55:24 +03:00 committed by Tony Lindgren
parent 7e45f17998
commit 7a825cc885
1 changed files with 36 additions and 0 deletions

View File

@ -2641,6 +2641,34 @@ static struct omap_hwmod dra7xx_des_hwmod = {
},
};
/* rng */
static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
.name = "rng",
.sysc = &dra7xx_rng_sysc,
};
static struct omap_hwmod dra7xx_rng_hwmod = {
.name = "rng",
.class = &dra7xx_rng_hwmod_class,
.flags = HWMOD_SWSUP_SIDLE,
.clkdm_name = "l4sec_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
*
@ -3798,6 +3826,13 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> rng */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_rng_hwmod,
.user = OCP_USER_MPU,
};
/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
.master = &dra7xx_l4_per3_hwmod,
@ -4028,6 +4063,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_wkup__timer12,
&dra7xx_l4_per1__rng,
NULL,
};