mirror of https://gitee.com/openkylin/linux.git
net: phy: mscc: configure both RX and TX internal delays for RGMII
The driver appears to be secretly enabling the RX clock skew irrespective of PHY interface type, which is generally considered a big no-no. Make them configurable instead, and add TX internal delays when necessary too. While at it, configure a more canonical clock skew of 2.0 nanoseconds than the current default of 1.1 ns. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -178,6 +178,8 @@ enum rgmii_clock_delay {
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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#define RGMII_TX_CLK_DELAY_MASK 0x0007
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#define RGMII_TX_CLK_DELAY_POS 0
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#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
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#define MSCC_PHY_WOL_MID_MAC_ADDR 22
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@ -522,16 +522,26 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev,
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static int vsc85xx_default_config(struct phy_device *phydev)
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{
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u16 reg_val = 0;
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int rc;
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u16 reg_val;
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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if (!phy_interface_mode_is_rgmii(phydev->interface))
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return 0;
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mutex_lock(&phydev->lock);
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reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS;
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rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
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MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
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MSCC_PHY_RGMII_CNTL,
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RGMII_RX_CLK_DELAY_MASK | RGMII_TX_CLK_DELAY_MASK,
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reg_val);
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mutex_unlock(&phydev->lock);
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