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[ARM] 4106/1: S3C2410: typo fixes in register definitions 

The Trcd* bits of the S3C24xx BANKCON6 and BANKCON7 registers are misspelled in include/asm-arm/arch-s3c2410/regs-mem.h as Trdc*.

Signed-off-by: Matt Reimer <mreimer@vpop.net>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Matt Reimer 2007-01-24 01:30:37 +01:00 committed by Russell King
parent d4e1c889c1
commit 7baced8a59
1 changed files with 7 additions and 7 deletions
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14
include/asm-arm/arch-s3c2410/regs-mem.h
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@ -133,10 +133,10 @@
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
/* next bits only for EDO DRAM in 6,7 */
#define S3C2400_BANKCON_EDO_Trdc1 (0x00 << 4)
#define S3C2400_BANKCON_EDO_Trdc2 (0x01 << 4)
#define S3C2400_BANKCON_EDO_Trdc3 (0x02 << 4)
#define S3C2400_BANKCON_EDO_Trdc4 (0x03 << 4)
#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
/* CAS pulse width */
#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
@ -153,9 +153,9 @@
#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trdc2 (0x00 << 2)
#define S3C2410_BANKCON_Trdc3 (0x01 << 2)
#define S3C2410_BANKCON_Trdc4 (0x02 << 2)
#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
/* control column address select */
#define S3C2410_BANKCON_SCANb8 (0x00 << 0)