mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: Support PSP VMR ring for Vega10 VF
Add VMR ring support for Vega10 SR-IOV VF if PSP supported Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Trigger Huang
Alex Deucher
parent
470b425019
commit
7bd877692e
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@ -50,6 +50,10 @@ MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
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static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};
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static bool psp_v3_1_support_vmr_ring(struct psp_context *psp);
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static int psp_v3_1_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type);
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static int psp_v3_1_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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@ -296,27 +300,57 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
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psp_v3_1_reroute_ih(psp);
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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if (psp_v3_1_support_vmr_ring(psp)) {
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ret = psp_v3_1_ring_stop(psp, ring_type);
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if (ret) {
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DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
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return ret;
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}
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Write low address of the ring to C2PMSG_102 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_103 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
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/* No size initialization for sriov */
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/* Write the ring initialization command to C2PMSG_101 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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/* there might be hardware handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
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mmMP0_SMN_C2PMSG_101), 0x80000000,
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0x8000FFFF, false);
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} else {
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be hardware handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
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mmMP0_SMN_C2PMSG_64), 0x80000000,
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0x8000FFFF, false);
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}
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return ret;
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}
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@ -327,16 +361,31 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,
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unsigned int psp_ring_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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/* Write the ring destroy command to C2PMSG_64 */
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psp_ring_reg = 3 << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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if (psp_v3_1_support_vmr_ring(psp)) {
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/* Write the Destroy GPCOM ring command to C2PMSG_101 */
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psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* there might be handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp,
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SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
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0x80000000, 0x80000000, false);
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} else {
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/* Write the ring destroy command to C2PMSG_64 */
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psp_ring_reg = 3 << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp,
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SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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}
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return ret;
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}
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@ -375,7 +424,10 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp,
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uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
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/* KM (GPCOM) prepare write pointer */
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psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
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if (psp_v3_1_support_vmr_ring(psp))
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psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
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else
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psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
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/* Update KM RB frame pointer to new frame */
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/* write_frame ptr increments by size of rb_frame in bytes */
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@ -404,7 +456,13 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp,
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/* Update the write Pointer in DWORDs */
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psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
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if (psp_v3_1_support_vmr_ring(psp)) {
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
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/* send interrupt to PSP for SRIOV ring write pointer update */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_CONSUME_CMD);
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} else
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
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return 0;
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}
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@ -574,6 +632,14 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
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return 0;
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}
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static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
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{
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if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455)
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return true;
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return false;
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}
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static const struct psp_funcs psp_v3_1_funcs = {
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.init_microcode = psp_v3_1_init_microcode,
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.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
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@ -586,6 +652,7 @@ static const struct psp_funcs psp_v3_1_funcs = {
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.compare_sram_data = psp_v3_1_compare_sram_data,
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.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
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.mode1_reset = psp_v3_1_mode1_reset,
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.support_vmr_ring = psp_v3_1_support_vmr_ring,
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};
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void psp_v3_1_set_psp_funcs(struct psp_context *psp)
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