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arm64: dts: imx8qxp: add cpu opp table 

Add i.MX8QXP CPU opp table to support cpufreq.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Anson Huang 2019-02-26 05:17:31 +00:00 committed by Shawn Guo
parent 9e98c678c2
commit 7be494dd81
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
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@ -34,6 +34,9 @@ A35_0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_1: cpu@1 {
@ -42,6 +45,9 @@ A35_1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_2: cpu@2 {
@ -50,6 +56,9 @@ A35_2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_3: cpu@3 {
@ -58,6 +67,9 @@ A35_3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_L2: l2-cache0 {
@ -65,6 +77,24 @@ A35_L2: l2-cache0 {
};
};
a35_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */