mirror of https://gitee.com/openkylin/linux.git
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(), *GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances with intel_gpu_freq() and intel_freq_opcode() calls. Most of the change was performed with the following semantic patch: @@ expression E; @@ ( - E * GT_FREQUENCY_MULTIPLIER + intel_gpu_freq(dev_priv, E) | - E *= GT_FREQUENCY_MULTIPLIER + E = intel_gpu_freq(dev_priv, E) | - E /= GT_FREQUENCY_MULTIPLIER + E = intel_freq_opcode(dev_priv, E) | - do_div(E, GT_FREQUENCY_MULTIPLIER) + E = intel_freq_opcode(dev_priv, E) ) @@ expression E1, E2; @@ ( - vlv_gpu_freq(E1, E2) + intel_gpu_freq(E1, E2) | - vlv_freq_opcode(E1, E2) + intel_freq_opcode(E1, E2) ) @@ expression E1, E2, E3, E4; @@ ( - if (IS_VALLEYVIEW(E1)) { - E2 = intel_gpu_freq(E3, E4); - } else { - E2 = intel_gpu_freq(E3, E4); - } + E2 = intel_gpu_freq(E3, E4); | - if (IS_VALLEYVIEW(E1)) { - E2 = intel_freq_opcode(E3, E4); - } else { - E2 = intel_freq_opcode(E3, E4); - } + E2 = intel_freq_opcode(E3, E4); ) One hunk was manually undone as intel_gpu_freq() ended up calling itself. Supposedly it would be possible to exclude certain functions via !=~, but I couldn't get that to work. Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat wrappers was done manually. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
616bc8202d
commit
7c59a9c133
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@ -1113,7 +1113,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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reqf >>= 24;
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else
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reqf >>= 25;
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reqf *= GT_FREQUENCY_MULTIPLIER;
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reqf = intel_gpu_freq(dev_priv, reqf);
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rpmodectl = I915_READ(GEN6_RP_CONTROL);
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rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
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@ -1130,7 +1130,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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else
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cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
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cagf *= GT_FREQUENCY_MULTIPLIER;
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cagf = intel_gpu_freq(dev_priv, cagf);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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mutex_unlock(&dev->struct_mutex);
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@ -1178,18 +1178,18 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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max_freq = (rp_state_cap & 0xff0000) >> 16;
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seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
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max_freq * GT_FREQUENCY_MULTIPLIER);
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = (rp_state_cap & 0xff00) >> 8;
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seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
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max_freq * GT_FREQUENCY_MULTIPLIER);
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = rp_state_cap & 0xff;
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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max_freq * GT_FREQUENCY_MULTIPLIER);
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intel_gpu_freq(dev_priv, max_freq));
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seq_printf(m, "Max overclocked frequency: %dMHz\n",
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dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
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intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
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} else if (IS_VALLEYVIEW(dev)) {
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u32 freq_sts;
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@ -1199,16 +1199,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
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seq_printf(m, "max GPU freq: %d MHz\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
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intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
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seq_printf(m, "min GPU freq: %d MHz\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
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intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
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seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
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seq_printf(m,
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"efficient (RPe) frequency: %d MHz\n",
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intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
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seq_printf(m, "current GPU freq: %d MHz\n",
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vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
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intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
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mutex_unlock(&dev_priv->rps.hw_lock);
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} else {
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seq_puts(m, "no P-state info available\n");
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@ -1677,7 +1678,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&ia_freq);
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seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
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gpu_freq * GT_FREQUENCY_MULTIPLIER,
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intel_gpu_freq(dev_priv, gpu_freq),
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((ia_freq >> 0) & 0xff) * 100,
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((ia_freq >> 8) & 0xff) * 100);
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}
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@ -4119,10 +4120,7 @@ i915_max_freq_get(void *data, u64 *val)
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if (ret)
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return ret;
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if (IS_VALLEYVIEW(dev))
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*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
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else
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*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
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*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return 0;
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@ -4151,12 +4149,12 @@ i915_max_freq_set(void *data, u64 val)
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* Turbo will still be enabled, but won't go above the set value.
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*/
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if (IS_VALLEYVIEW(dev)) {
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val = vlv_freq_opcode(dev_priv, val);
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val = intel_freq_opcode(dev_priv, val);
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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} else {
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do_div(val, GT_FREQUENCY_MULTIPLIER);
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val = intel_freq_opcode(dev_priv, val);
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.max_freq;
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@ -4200,10 +4198,7 @@ i915_min_freq_get(void *data, u64 *val)
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if (ret)
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return ret;
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if (IS_VALLEYVIEW(dev))
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*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
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else
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*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
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*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return 0;
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@ -4232,12 +4227,12 @@ i915_min_freq_set(void *data, u64 val)
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* Turbo will still be enabled, but won't go below the set value.
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*/
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if (IS_VALLEYVIEW(dev)) {
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val = vlv_freq_opcode(dev_priv, val);
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val = intel_freq_opcode(dev_priv, val);
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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} else {
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do_div(val, GT_FREQUENCY_MULTIPLIER);
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val = intel_freq_opcode(dev_priv, val);
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.max_freq;
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@ -3236,8 +3236,6 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
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int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
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int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
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int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
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int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
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#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
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#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
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@ -297,14 +297,14 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
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if (IS_VALLEYVIEW(dev_priv->dev)) {
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u32 freq;
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freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
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ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
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ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
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} else {
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u32 rpstat = I915_READ(GEN6_RPSTAT1);
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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else
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ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
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ret *= GT_FREQUENCY_MULTIPLIER;
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ret = intel_gpu_freq(dev_priv, ret);
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}
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -326,11 +326,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev)) {
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ret = vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
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} else {
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ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
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}
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ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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@ -345,8 +341,9 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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return snprintf(buf, PAGE_SIZE, "%d\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
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return snprintf(buf, PAGE_SIZE,
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"%d\n",
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intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
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}
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static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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flush_delayed_work(&dev_priv->rps.delayed_resume_work);
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev))
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ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
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else
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ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
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ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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@ -386,10 +380,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev))
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val = vlv_freq_opcode(dev_priv, val);
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else
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val /= GT_FREQUENCY_MULTIPLIER;
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val = intel_freq_opcode(dev_priv, val);
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if (val < dev_priv->rps.min_freq ||
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val > dev_priv->rps.max_freq ||
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if (val > dev_priv->rps.rp0_freq)
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DRM_DEBUG("User requested overclocking to %d\n",
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val * GT_FREQUENCY_MULTIPLIER);
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intel_gpu_freq(dev_priv, val));
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dev_priv->rps.max_freq_softlimit = val;
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flush_delayed_work(&dev_priv->rps.delayed_resume_work);
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev))
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ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
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else
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ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
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ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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@ -458,10 +446,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev))
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val = vlv_freq_opcode(dev_priv, val);
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else
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val /= GT_FREQUENCY_MULTIPLIER;
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val = intel_freq_opcode(dev_priv, val);
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if (val < dev_priv->rps.min_freq ||
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val > dev_priv->rps.max_freq ||
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@ -521,19 +506,22 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
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if (attr == &dev_attr_gt_RP0_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
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else
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val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0x0000ff) >> 0));
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} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
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else
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val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0x00ff00) >> 8));
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} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
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val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
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else
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val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0xff0000) >> 16));
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} else {
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BUG();
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}
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@ -3883,7 +3883,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
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I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
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dev_priv->rps.cur_freq = val;
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trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
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trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
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}
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static void gen9_disable_rps(struct drm_device *dev)
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@ -4619,22 +4619,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
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dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
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dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
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DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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dev_priv->rps.max_freq);
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dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
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DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
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DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
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dev_priv->rps.rp1_freq);
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dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
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DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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dev_priv->rps.min_freq);
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/* Preserve min/max settings in case of re-init */
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@ -4688,22 +4688,22 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
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dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
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dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
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DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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dev_priv->rps.max_freq);
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dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
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DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
|
||||
DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
|
||||
dev_priv->rps.rp1_freq);
|
||||
|
||||
dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
|
||||
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
|
||||
dev_priv->rps.min_freq);
|
||||
|
||||
WARN_ONCE((dev_priv->rps.max_freq |
|
||||
|
@ -4807,11 +4807,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
|
|||
|
||||
dev_priv->rps.cur_freq = (val >> 8) & 0xff;
|
||||
DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
|
||||
dev_priv->rps.cur_freq);
|
||||
|
||||
DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
||||
dev_priv->rps.efficient_freq);
|
||||
|
||||
valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
|
||||
|
@ -4891,11 +4891,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
|
|||
|
||||
dev_priv->rps.cur_freq = (val >> 8) & 0xff;
|
||||
DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
|
||||
dev_priv->rps.cur_freq);
|
||||
|
||||
DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
|
||||
vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
||||
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
||||
dev_priv->rps.efficient_freq);
|
||||
|
||||
valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
|
||||
|
@ -6625,11 +6625,6 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
|||
return val * GT_FREQUENCY_MULTIPLIER;
|
||||
}
|
||||
|
||||
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
||||
{
|
||||
return intel_gpu_freq(dev_priv, val);
|
||||
}
|
||||
|
||||
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
||||
{
|
||||
if (IS_CHERRYVIEW(dev_priv->dev))
|
||||
|
@ -6640,11 +6635,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
|||
return val / GT_FREQUENCY_MULTIPLIER;
|
||||
}
|
||||
|
||||
int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
||||
{
|
||||
return intel_freq_opcode(dev_priv, val);
|
||||
}
|
||||
|
||||
void intel_pm_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
Loading…
Reference in New Issue