mirror of https://gitee.com/openkylin/linux.git
drm/i915: Extract the HSW DDI selection code into its own function
Future platform will slightly change that. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -7607,6 +7607,22 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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return 0;
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}
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static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
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enum port port,
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struct intel_crtc_config *pipe_config)
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{
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pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
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switch (pipe_config->ddi_pll_sel) {
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case PORT_CLK_SEL_WRPLL1:
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pipe_config->shared_dpll = DPLL_ID_WRPLL1;
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break;
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case PORT_CLK_SEL_WRPLL2:
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pipe_config->shared_dpll = DPLL_ID_WRPLL2;
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break;
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}
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}
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static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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@ -7620,16 +7636,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
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port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
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pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
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switch (pipe_config->ddi_pll_sel) {
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case PORT_CLK_SEL_WRPLL1:
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pipe_config->shared_dpll = DPLL_ID_WRPLL1;
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break;
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case PORT_CLK_SEL_WRPLL2:
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pipe_config->shared_dpll = DPLL_ID_WRPLL2;
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break;
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}
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haswell_get_ddi_pll(dev_priv, port, pipe_config);
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if (pipe_config->shared_dpll >= 0) {
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pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
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