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Amlogic 32-bit DT updates for v4.18 

- add support for meson8m2 SoC
 - new board: Tronsmart MXIII Plus using meson8m2 SoC
 - odroid-c1: add IR
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Merge tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Amlogic 32-bit DT updates for v4.18
- add support for meson8m2 SoC
- new board: Tronsmart MXIII Plus using meson8m2 SoC
- odroid-c1: add IR

* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson8m2: add support for the Tronsmart MXIII Plus
  ARM: dts: meson8: add the uart_A pins
  ARM: dts: meson: add support for the Meson8m2 SoC
  ARM: meson: add support for the Meson8m2 SoCs
  ARM: dts: meson8b: odroid-c1: enable the IR receiver
  ARM: dts: meson8b: odroid-c1: sort nodes alphabetically
  ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
  ARM: dts: meson8: add the cortex-a9-pmu compatible PMU

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-05-25 04:47:45 -07:00
parent 3c13e601a2 35ee52bea6
commit 7d6020cf27
8 changed files with 412 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/Makefile
View File

@ -313,7 +313,8 @@ dtb-$(CONFIG_ARCH_NPCM7XX) += \
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
meson8-minix-neo-x8.dtb
meson8-minix-neo-x8.dtb \
meson8m2-mxiii-plus.dtb
dtb-$(CONFIG_ARCH_MMP) += \
pxa168-aspenite.dtb \
pxa910-dkb.dtb \

33
arch/arm/boot/dts/meson8.dtsi
View File

@ -57,7 +57,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@200 {
cpu0: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@ -66,7 +66,7 @@ cpu@200 {
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
cpu@201 {
cpu1: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@ -75,7 +75,7 @@ cpu@201 {
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
cpu@202 {
cpu2: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@ -84,7 +84,7 @@ cpu@202 {
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
cpu@203 {
cpu3: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@ -94,6 +94,15 @@ cpu@203 {
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@ -272,6 +281,22 @@ mux {
function = "pwm_e";
};
};
uart_a1_pins: uart-a1 {
mux {
groups = "uart_tx_a1",
"uart_rx_a1";
function = "uart_a";
};
};
uart_a1_cts_rts_pins: uart-a1-cts-rts {
mux {
groups = "uart_cts_a1",
"uart_rts_a1";
function = "uart_a";
};
};
};
};

116
arch/arm/boot/dts/meson8b-odroidc1.dts
View File

@ -103,61 +103,6 @@ tf_io: gpio-regulator-tf_io {
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
* to be turned high in order to be detected by the USB Controller.
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
};
&sdio {
status = "okay";
pinctrl-0 = <&sd_b_pins>;
pinctrl-names = "default";
/* SD card */
sd_card_slot: slot@1 {
compatible = "mmc-slot";
reg = <1>;
status = "okay";
bus-width = <4>;
no-sdio;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
};
&ethmac {
status = "okay";
@ -187,3 +132,64 @@ eth_phy: ethernet-phy@0 {
};
};
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
* to be turned high in order to be detected by the USB Controller.
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&ir_receiver {
status = "okay";
pinctrl-0 = <&ir_recv_pins>;
pinctrl-names = "default";
};
&sdio {
status = "okay";
pinctrl-0 = <&sd_b_pins>;
pinctrl-names = "default";
/* SD card */
sd_card_slot: slot@1 {
compatible = "mmc-slot";
reg = <1>;
status = "okay";
bus-width = <4>;
no-sdio;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
};

24
arch/arm/boot/dts/meson8b.dtsi
View File

@ -55,7 +55,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@200 {
cpu0: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -64,7 +64,7 @@ cpu@200 {
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
cpu@201 {
cpu1: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -73,7 +73,7 @@ cpu@201 {
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
cpu@202 {
cpu2: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -82,7 +82,7 @@ cpu@202 {
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
cpu@203 {
cpu3: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -92,6 +92,15 @@ cpu@203 {
};
};
pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@ -139,6 +148,13 @@ mux {
function = "uart_ao";
};
};
ir_recv_pins: remote {
mux {
groups = "remote_input";
function = "remote";
};
};
};
};

244
arch/arm/boot/dts/meson8m2-mxiii-plus.dts Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru>
* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
/dts-v1/;
#include "meson8m2.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Tronsmart MXIII Plus";
compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2";
aliases {
ethernet0 = &ethmac;
i2c0 = &i2c_AO;
serial0 = &uart_AO;
serial1 = &uart_A;
mmc0 = &sd_card_slot;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x40000000 0x80000000>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1710000>;
button-function {
label = "Function";
linux,code = <KEY_FN>;
press-threshold-microvolt = <10000>;
};
};
vcc_3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cpu0 {
cpu-supply = <&vcck>;
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <4>;
snps,reset-gpio = <&gpio GPIOH_4 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
};
&ir_receiver {
status = "okay";
pinctrl-0 = <&ir_recv_pins>;
pinctrl-names = "default";
};
&i2c_AO {
status = "okay";
pinctrl-0 = <&i2c_ao_pins>;
pinctrl-names = "default";
pmic@32 {
compatible = "ricoh,rn5t618";
reg = <0x32>;
system-power-controller;
regulators {
vcck: DCDC1 {
regulator-name = "VCCK";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
DCDC2 {
regulator-name = "VDDAO";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
DCDC3 {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
LDO1 {
regulator-name = "VDDIO_AO28";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-boot-on;
regulator-always-on;
};
vddio_ao1v8: LDO2 {
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
LDO3 {
regulator-name = "VCC1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
LDO4 {
regulator-name = "VCC2V8";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
regulator-always-on;
};
LDO5 {
regulator-name = "AVDD1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
LDORTC1 {
regulator-name = "VDD_LDO";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-boot-on;
regulator-always-on;
};
LDORTC2 {
regulator-name = "RTC_0V9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao1v8>;
};
&sdio {
status = "okay";
pinctrl-0 = <&sd_b_pins>;
pinctrl-names = "default";
/* SD card */
sd_card_slot: slot@1 {
compatible = "mmc-slot";
reg = <1>;
status = "okay";
bus-width = <4>;
no-sdio;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vcc_3v3>;
};
};
/* connected to the Bluetooth module */
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};

54
arch/arm/boot/dts/meson8m2.dtsi Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
*/
#include "meson8.dtsi"
/ {
model = "Amlogic Meson8m2 SoC";
compatible = "amlogic,meson8m2";
}; /* end of / */
&clkc {
compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
};
&ethmac {
compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
0xc1108140 0x8>;
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
};
&pinctrl_aobus {
compatible = "amlogic,meson8m2-aobus-pinctrl",
"amlogic,meson8-aobus-pinctrl";
};
&pinctrl_cbus {
compatible = "amlogic,meson8m2-cbus-pinctrl",
"amlogic,meson8-cbus-pinctrl";
eth_rgmii_pins: ethernet {
mux {
groups = "eth_tx_clk_50m", "eth_tx_en",
"eth_txd3", "eth_txd2",
"eth_txd1", "eth_txd0",
"eth_rx_clk_in", "eth_rx_dv",
"eth_rxd3", "eth_rxd2",
"eth_rxd1", "eth_rxd0",
"eth_mdio", "eth_mdc";
function = "ethernet";
};
};
};
&wdt {
compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
};

2
arch/arm/mach-meson/Kconfig
View File

@ -19,7 +19,7 @@ config MACH_MESON6
select MESON6_TIMER
config MACH_MESON8
bool "Amlogic Meson8 SoCs support"
bool "Amlogic Meson8 and Meson8m2 SoCs support"
default ARCH_MESON
select MESON6_TIMER
select COMMON_CLK_MESON8B

1
arch/arm/mach-meson/meson.c
View File

@ -20,6 +20,7 @@ static const char * const meson_common_board_compat[] = {
"amlogic,meson6",
"amlogic,meson8",
"amlogic,meson8b",
"amlogic,meson8m2",
NULL,
};