mirror of https://gitee.com/openkylin/linux.git
8250: Serial driver changes to support future Cavium OCTEON serial patches.
In order to use Cavium OCTEON specific serial i/o drivers, we first patch the 8250 driver to use replaceable I/O functions. Compatible I/O functions are added for existing iotypeS. An added benefit of this change is that it makes it easy to factor some of the existing special cases out to board/SOC specific support code. The alternative is to load up 8250.c with a bunch of OCTEON specific iotype code and bug work-arounds. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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7d6a07d123
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@ -303,16 +303,16 @@ static const u8 au_io_out_map[] = {
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};
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/* sane hardware needs no mapping */
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static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
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static inline int map_8250_in_reg(struct uart_port *p, int offset)
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{
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if (up->port.iotype != UPIO_AU)
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if (p->iotype != UPIO_AU)
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return offset;
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return au_io_in_map[offset];
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}
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static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
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static inline int map_8250_out_reg(struct uart_port *p, int offset)
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{
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if (up->port.iotype != UPIO_AU)
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if (p->iotype != UPIO_AU)
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return offset;
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return au_io_out_map[offset];
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}
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@ -341,16 +341,16 @@ static const u8
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[UART_SCR] = 0x2c
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};
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static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
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static inline int map_8250_in_reg(struct uart_port *p, int offset)
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{
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if (up->port.iotype != UPIO_RM9000)
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if (p->iotype != UPIO_RM9000)
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return offset;
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return regmap_in[offset];
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}
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static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
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static inline int map_8250_out_reg(struct uart_port *p, int offset)
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{
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if (up->port.iotype != UPIO_RM9000)
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if (p->iotype != UPIO_RM9000)
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return offset;
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return regmap_out[offset];
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}
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@ -363,108 +363,170 @@ static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
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#endif
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static unsigned int serial_in(struct uart_8250_port *up, int offset)
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static unsigned int hub6_serial_in(struct uart_port *p, int offset)
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{
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unsigned int tmp;
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offset = map_8250_in_reg(up, offset) << up->port.regshift;
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switch (up->port.iotype) {
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case UPIO_HUB6:
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outb(up->port.hub6 - 1 + offset, up->port.iobase);
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return inb(up->port.iobase + 1);
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case UPIO_MEM:
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case UPIO_DWAPB:
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return readb(up->port.membase + offset);
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case UPIO_RM9000:
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case UPIO_MEM32:
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return readl(up->port.membase + offset);
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#ifdef CONFIG_SERIAL_8250_AU1X00
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case UPIO_AU:
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return __raw_readl(up->port.membase + offset);
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#endif
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case UPIO_TSI:
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if (offset == UART_IIR) {
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tmp = readl(up->port.membase + (UART_IIR & ~3));
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return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
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} else
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return readb(up->port.membase + offset);
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default:
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return inb(up->port.iobase + offset);
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}
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offset = map_8250_in_reg(p, offset) << p->regshift;
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outb(p->hub6 - 1 + offset, p->iobase);
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return inb(p->iobase + 1);
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}
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static void
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serial_out(struct uart_8250_port *up, int offset, int value)
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static void hub6_serial_out(struct uart_port *p, int offset, int value)
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{
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/* Save the offset before it's remapped */
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int save_offset = offset;
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offset = map_8250_out_reg(up, offset) << up->port.regshift;
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offset = map_8250_out_reg(p, offset) << p->regshift;
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outb(p->hub6 - 1 + offset, p->iobase);
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outb(value, p->iobase + 1);
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}
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switch (up->port.iotype) {
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static unsigned int mem_serial_in(struct uart_port *p, int offset)
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{
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offset = map_8250_in_reg(p, offset) << p->regshift;
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return readb(p->membase + offset);
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}
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static void mem_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = map_8250_out_reg(p, offset) << p->regshift;
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writeb(value, p->membase + offset);
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}
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static void mem32_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = map_8250_out_reg(p, offset) << p->regshift;
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writel(value, p->membase + offset);
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}
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static unsigned int mem32_serial_in(struct uart_port *p, int offset)
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{
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offset = map_8250_in_reg(p, offset) << p->regshift;
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return readl(p->membase + offset);
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}
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#ifdef CONFIG_SERIAL_8250_AU1X00
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static unsigned int au_serial_in(struct uart_port *p, int offset)
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{
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offset = map_8250_in_reg(p, offset) << p->regshift;
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return __raw_readl(p->membase + offset);
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}
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static void au_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = map_8250_out_reg(p, offset) << p->regshift;
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__raw_writel(value, p->membase + offset);
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}
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#endif
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static unsigned int tsi_serial_in(struct uart_port *p, int offset)
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{
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unsigned int tmp;
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offset = map_8250_in_reg(p, offset) << p->regshift;
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if (offset == UART_IIR) {
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tmp = readl(p->membase + (UART_IIR & ~3));
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return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
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} else
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return readb(p->membase + offset);
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}
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static void tsi_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = map_8250_out_reg(p, offset) << p->regshift;
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if (!((offset == UART_IER) && (value & UART_IER_UUE)))
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writeb(value, p->membase + offset);
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}
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static void dwapb_serial_out(struct uart_port *p, int offset, int value)
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{
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int save_offset = offset;
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offset = map_8250_out_reg(p, offset) << p->regshift;
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/* Save the LCR value so it can be re-written when a
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* Busy Detect interrupt occurs. */
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if (save_offset == UART_LCR) {
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struct uart_8250_port *up = (struct uart_8250_port *)p;
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up->lcr = value;
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}
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writeb(value, p->membase + offset);
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/* Read the IER to ensure any interrupt is cleared before
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* returning from ISR. */
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if (save_offset == UART_TX || save_offset == UART_IER)
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value = p->serial_in(p, UART_IER);
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}
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static unsigned int io_serial_in(struct uart_port *p, int offset)
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{
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offset = map_8250_in_reg(p, offset) << p->regshift;
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return inb(p->iobase + offset);
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}
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static void io_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = map_8250_out_reg(p, offset) << p->regshift;
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outb(value, p->iobase + offset);
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}
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static void set_io_from_upio(struct uart_port *p)
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{
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switch (p->iotype) {
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case UPIO_HUB6:
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outb(up->port.hub6 - 1 + offset, up->port.iobase);
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outb(value, up->port.iobase + 1);
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p->serial_in = hub6_serial_in;
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p->serial_out = hub6_serial_out;
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break;
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case UPIO_MEM:
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writeb(value, up->port.membase + offset);
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p->serial_in = mem_serial_in;
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p->serial_out = mem_serial_out;
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break;
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case UPIO_RM9000:
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case UPIO_MEM32:
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writel(value, up->port.membase + offset);
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p->serial_in = mem32_serial_in;
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p->serial_out = mem32_serial_out;
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break;
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#ifdef CONFIG_SERIAL_8250_AU1X00
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case UPIO_AU:
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__raw_writel(value, up->port.membase + offset);
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p->serial_in = au_serial_in;
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p->serial_out = au_serial_out;
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break;
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#endif
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case UPIO_TSI:
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if (!((offset == UART_IER) && (value & UART_IER_UUE)))
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writeb(value, up->port.membase + offset);
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p->serial_in = tsi_serial_in;
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p->serial_out = tsi_serial_out;
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break;
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case UPIO_DWAPB:
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/* Save the LCR value so it can be re-written when a
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* Busy Detect interrupt occurs. */
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if (save_offset == UART_LCR)
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up->lcr = value;
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writeb(value, up->port.membase + offset);
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/* Read the IER to ensure any interrupt is cleared before
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* returning from ISR. */
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if (save_offset == UART_TX || save_offset == UART_IER)
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value = serial_in(up, UART_IER);
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p->serial_in = mem_serial_in;
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p->serial_out = dwapb_serial_out;
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break;
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default:
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outb(value, up->port.iobase + offset);
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p->serial_in = io_serial_in;
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p->serial_out = io_serial_out;
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break;
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}
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}
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static void
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serial_out_sync(struct uart_8250_port *up, int offset, int value)
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{
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switch (up->port.iotype) {
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struct uart_port *p = &up->port;
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switch (p->iotype) {
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case UPIO_MEM:
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case UPIO_MEM32:
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#ifdef CONFIG_SERIAL_8250_AU1X00
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case UPIO_AU:
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#endif
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case UPIO_DWAPB:
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serial_out(up, offset, value);
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serial_in(up, UART_LCR); /* safe, no side-effects */
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p->serial_out(p, offset, value);
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p->serial_in(p, UART_LCR); /* safe, no side-effects */
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break;
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default:
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serial_out(up, offset, value);
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p->serial_out(p, offset, value);
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}
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}
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#define serial_in(up, offset) \
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(up->port.serial_in(&(up)->port, (offset)))
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#define serial_out(up, offset, value) \
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(up->port.serial_out(&(up)->port, (offset), (value)))
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/*
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* We used to support using pause I/O for certain machines. We
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* haven't supported this for a while, but just in case it's badly
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@ -2576,6 +2638,7 @@ static void __init serial8250_isa_init_ports(void)
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up->port.membase = old_serial_port[i].iomem_base;
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up->port.iotype = old_serial_port[i].io_type;
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up->port.regshift = old_serial_port[i].iomem_reg_shift;
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set_io_from_upio(&up->port);
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if (share_irqs)
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up->port.flags |= UPF_SHARE_IRQ;
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}
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@ -2769,6 +2832,13 @@ int __init early_serial_setup(struct uart_port *port)
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p->flags = port->flags;
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p->mapbase = port->mapbase;
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p->private_data = port->private_data;
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set_io_from_upio(p);
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if (port->serial_in)
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p->serial_in = port->serial_in;
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if (port->serial_out)
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p->serial_out = port->serial_out;
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return 0;
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}
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@ -2833,6 +2903,8 @@ static int __devinit serial8250_probe(struct platform_device *dev)
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port.mapbase = p->mapbase;
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port.hub6 = p->hub6;
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port.private_data = p->private_data;
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port.serial_in = p->serial_in;
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port.serial_out = p->serial_out;
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port.dev = &dev->dev;
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if (share_irqs)
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port.flags |= UPF_SHARE_IRQ;
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@ -2986,6 +3058,12 @@ int serial8250_register_port(struct uart_port *port)
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uart->port.private_data = port->private_data;
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if (port->dev)
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uart->port.dev = port->dev;
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set_io_from_upio(&uart->port);
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/* Possibly override default I/O functions. */
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if (port->serial_in)
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uart->port.serial_in = port->serial_in;
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if (port->serial_out)
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uart->port.serial_out = port->serial_out;
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ret = uart_add_one_port(&serial8250_reg, &uart->port);
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if (ret == 0)
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@ -28,6 +28,8 @@ struct plat_serial8250_port {
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unsigned char iotype; /* UPIO_* */
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unsigned char hub6;
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upf_t flags; /* UPF_* flags */
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unsigned int (*serial_in)(struct uart_port *, int);
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void (*serial_out)(struct uart_port *, int, int);
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};
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/*
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@ -248,6 +248,8 @@ struct uart_port {
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spinlock_t lock; /* port lock */
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unsigned long iobase; /* in/out[bwl] */
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unsigned char __iomem *membase; /* read/write[bwl] */
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unsigned int (*serial_in)(struct uart_port *, int);
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void (*serial_out)(struct uart_port *, int, int);
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unsigned int irq; /* irq number */
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unsigned int uartclk; /* base uart clock */
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unsigned int fifosize; /* tx fifo size */
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