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drm/i915: Add missing platform tags to FBC workaround comments 

There was a race between Rodrigo writing those patches and me
formalizing the addition of platform tags. This patches fixes it.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2013-05-10 14:33:17 +01:00 committed by Daniel Vetter
parent 7881d4f11c
commit 7dd23ba089
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/i915/intel_pm.c
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@ -243,13 +243,13 @@ static void ironlake_disable_fbc(struct drm_device *dev)
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
if (IS_IVYBRIDGE(dev)) if (IS_IVYBRIDGE(dev))
/* WaFbcDisableDpfcClockGating */ /* WaFbcDisableDpfcClockGating:ivb */
I915_WRITE(ILK_DSPCLK_GATE_D, I915_WRITE(ILK_DSPCLK_GATE_D,
I915_READ(ILK_DSPCLK_GATE_D) & I915_READ(ILK_DSPCLK_GATE_D) &
~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
if (IS_HASWELL(dev)) if (IS_HASWELL(dev))
/* WaFbcDisableDpfcClockGating */ /* WaFbcDisableDpfcClockGating:hsw */
I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
I915_READ(HSW_CLKGATE_DISABLE_PART_1) & I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
~HSW_DPFC_GATING_DISABLE); ~HSW_DPFC_GATING_DISABLE);
@ -281,17 +281,17 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(dev)) {
/* WaFbcAsynchFlipDisableFbcQueue */ /* WaFbcAsynchFlipDisableFbcQueue:ivb */
I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
/* WaFbcDisableDpfcClockGating */ /* WaFbcDisableDpfcClockGating:ivb */
I915_WRITE(ILK_DSPCLK_GATE_D, I915_WRITE(ILK_DSPCLK_GATE_D,
I915_READ(ILK_DSPCLK_GATE_D) | I915_READ(ILK_DSPCLK_GATE_D) |
ILK_DPFCUNIT_CLOCK_GATE_DISABLE); ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
} else { } else {
/* WaFbcAsynchFlipDisableFbcQueue */ /* WaFbcAsynchFlipDisableFbcQueue:hsw */
I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
HSW_BYPASS_FBC_QUEUE); HSW_BYPASS_FBC_QUEUE);
/* WaFbcDisableDpfcClockGating */ /* WaFbcDisableDpfcClockGating:hsw */
I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
I915_READ(HSW_CLKGATE_DISABLE_PART_1) | I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
HSW_DPFC_GATING_DISABLE); HSW_DPFC_GATING_DISABLE);