mirror of https://gitee.com/openkylin/linux.git
net: dsa: felix: use resolved link config in mac_link_up()
Phylink now requires that parameters established through auto-negotiation be written into the MAC at the time of the mac_link_up() callback. In the case of felix, that means taking the port out of reset, setting the correct timers for PAUSE frames, and enabling/disabling TX flow control. This patch also splits the inband and noinband configuration of the vsc9959 PCS (currently found in a function called "init") into 2 different functions, which have a nomenclature closer to phylink: "config", for inband setup, and "link_up", for noinband (forced) setup. This is necessary as a preparation step for giving up control of the PCS to phylink, which will be done in further patch series. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
David S. Miller
parent
b4c2354537
commit
7e14a2dc8c
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@ -235,65 +235,10 @@ static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
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const struct phylink_link_state *state)
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{
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struct ocelot *ocelot = ds->priv;
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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struct felix *felix = ocelot_to_felix(ocelot);
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u32 mac_fc_cfg;
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/* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
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* PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is
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* integrated is that the MAC speed is fixed and it's the PCS who is
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* performing the rate adaptation, so we have to write "1000Mbps" into
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* the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default
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* value).
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*/
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ocelot_port_writel(ocelot_port,
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DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
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DEV_CLOCK_CFG);
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switch (state->speed) {
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case SPEED_10:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
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break;
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case SPEED_100:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
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break;
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case SPEED_1000:
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case SPEED_2500:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
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break;
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case SPEED_UNKNOWN:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(0);
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break;
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default:
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dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
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port, state->speed);
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return;
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}
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/* handle Rx pause in all cases, with 2500base-X this is used for rate
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* adaptation.
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*/
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mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
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if (state->pause & MLO_PAUSE_TX)
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mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
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SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
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SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
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SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
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/* Flow control. Link speed is only used here to evaluate the time
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* specification in incoming pause frames.
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*/
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ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
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ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
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if (felix->info->pcs_init)
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felix->info->pcs_init(ocelot, port, link_an_mode, state);
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if (felix->info->port_sched_speed_set)
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felix->info->port_sched_speed_set(ocelot, port,
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state->speed);
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if (felix->info->pcs_config)
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felix->info->pcs_config(ocelot, port, link_an_mode, state);
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}
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static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port,
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@ -317,8 +262,58 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
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{
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struct ocelot *ocelot = ds->priv;
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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struct felix *felix = ocelot_to_felix(ocelot);
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u32 mac_fc_cfg;
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/* Enable MAC module */
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/* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
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* PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is
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* integrated is that the MAC speed is fixed and it's the PCS who is
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* performing the rate adaptation, so we have to write "1000Mbps" into
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* the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default
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* value).
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*/
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ocelot_port_writel(ocelot_port,
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DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
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DEV_CLOCK_CFG);
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switch (speed) {
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case SPEED_10:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
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break;
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case SPEED_100:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
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break;
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case SPEED_1000:
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case SPEED_2500:
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mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
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break;
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default:
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dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
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port, speed);
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return;
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}
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/* handle Rx pause in all cases, with 2500base-X this is used for rate
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* adaptation.
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*/
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mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
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if (tx_pause)
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mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
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SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
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SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
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SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
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/* Flow control. Link speed is only used here to evaluate the time
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* specification in incoming pause frames.
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*/
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ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
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ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
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/* Undo the effects of felix_phylink_mac_link_down:
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* enable MAC module
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*/
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ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
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DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
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@ -335,6 +330,13 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
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QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
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QSYS_SWITCH_PORT_MODE_PORT_ENA,
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QSYS_SWITCH_PORT_MODE, port);
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if (felix->info->pcs_link_up)
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felix->info->pcs_link_up(ocelot, port, link_an_mode, interface,
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speed, duplex);
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if (felix->info->port_sched_speed_set)
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felix->info->port_sched_speed_set(ocelot, port, speed);
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}
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static void felix_port_qos_map_init(struct ocelot *ocelot, int port)
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@ -28,9 +28,13 @@ struct felix_info {
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int imdio_pci_bar;
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int (*mdio_bus_alloc)(struct ocelot *ocelot);
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void (*mdio_bus_free)(struct ocelot *ocelot);
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void (*pcs_init)(struct ocelot *ocelot, int port,
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unsigned int link_an_mode,
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const struct phylink_link_state *state);
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void (*pcs_config)(struct ocelot *ocelot, int port,
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unsigned int link_an_mode,
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const struct phylink_link_state *state);
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void (*pcs_link_up)(struct ocelot *ocelot, int port,
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unsigned int link_an_mode,
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phy_interface_t interface,
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int speed, int duplex);
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void (*pcs_link_state)(struct ocelot *ocelot, int port,
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struct phylink_link_state *state);
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int (*prevalidate_phy_mode)(struct ocelot *ocelot, int port,
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@ -737,124 +737,54 @@ static int vsc9959_reset(struct ocelot *ocelot)
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* traffic if SGMII AN is enabled but not completed (acknowledged by us), so
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* setting MLO_AN_INBAND is actually required for those.
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*/
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static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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if (link_an_mode == MLO_AN_INBAND) {
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int bmsr, bmcr;
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/* Some PHYs like VSC8234 don't like it when AN restarts on
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* their system side and they restart line side AN too, going
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* into an endless link up/down loop. Don't restart PCS AN if
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* link is up already.
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* We do check that AN is enabled just in case this is the 1st
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* call, PCS detects a carrier but AN is disabled from power on
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* or by boot loader.
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*/
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bmcr = phy_read(pcs, MII_BMCR);
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if (bmcr < 0)
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return;
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bmsr = phy_read(pcs, MII_BMSR);
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if (bmsr < 0)
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return;
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if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS))
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return;
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/* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001
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* for the MAC PCS in order to acknowledge the AN.
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*/
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phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII |
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ADVERTISE_LPACK);
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phy_write(pcs, ENETC_PCS_IF_MODE,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_USE_SGMII_AN);
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/* Adjust link timer for SGMII */
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phy_write(pcs, ENETC_PCS_LINK_TIMER1,
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ENETC_PCS_LINK_TIMER1_VAL);
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phy_write(pcs, ENETC_PCS_LINK_TIMER2,
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ENETC_PCS_LINK_TIMER2_VAL);
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phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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} else {
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u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN;
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int speed;
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switch (state->speed) {
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case SPEED_1000:
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speed = ENETC_PCS_SPEED_1000;
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break;
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case SPEED_100:
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speed = ENETC_PCS_SPEED_100;
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break;
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case SPEED_10:
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speed = ENETC_PCS_SPEED_10;
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break;
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case SPEED_UNKNOWN:
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/* Silently don't do anything */
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return;
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default:
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phydev_err(pcs, "Invalid PCS speed %d\n", state->speed);
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return;
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}
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if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(speed);
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if (state->duplex == DUPLEX_HALF)
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if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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}
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/* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
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* clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
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* auto-negotiation of any link parameters. Electrically it is compatible with
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* a single lane of XAUI.
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* The hardware reference manual wants to call this mode SGMII, but it isn't
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* really, since the fundamental features of SGMII:
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* - Downgrading the link speed by duplicating symbols
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* - Auto-negotiation
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* are not there.
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* The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers
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* because the clock frequency is actually given by a PLL configured in the
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* Reset Configuration Word (RCW).
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* Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
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* AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
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* lower link speed on line side, the system-side interface remains fixed at
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* 2500 Mbps and we do rate adaptation through pause frames.
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*/
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static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) |
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ENETC_PCS_IF_MODE_SGMII_EN;
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if (link_an_mode == MLO_AN_INBAND) {
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phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
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return;
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}
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if (state->duplex == DUPLEX_HALF)
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if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
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phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs,
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static void vsc9959_pcs_config_sgmii(struct phy_device *pcs,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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if (link_an_mode != MLO_AN_INBAND) {
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phydev_err(pcs, "USXGMII only supports in-band AN for now\n");
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return;
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}
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int bmsr, bmcr;
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/* Some PHYs like VSC8234 don't like it when AN restarts on
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* their system side and they restart line side AN too, going
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* into an endless link up/down loop. Don't restart PCS AN if
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* link is up already.
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* We do check that AN is enabled just in case this is the 1st
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* call, PCS detects a carrier but AN is disabled from power on
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* or by boot loader.
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*/
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bmcr = phy_read(pcs, MII_BMCR);
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if (bmcr < 0)
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return;
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bmsr = phy_read(pcs, MII_BMSR);
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if (bmsr < 0)
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return;
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if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS))
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return;
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/* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001
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* for the MAC PCS in order to acknowledge the AN.
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*/
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phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII |
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ADVERTISE_LPACK);
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phy_write(pcs, ENETC_PCS_IF_MODE,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_USE_SGMII_AN);
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/* Adjust link timer for SGMII */
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phy_write(pcs, ENETC_PCS_LINK_TIMER1,
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ENETC_PCS_LINK_TIMER1_VAL);
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phy_write(pcs, ENETC_PCS_LINK_TIMER2,
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ENETC_PCS_LINK_TIMER2_VAL);
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phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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static void vsc9959_pcs_config_usxgmii(struct phy_device *pcs,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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/* Configure device ability for the USXGMII Replicator */
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phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE,
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USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) |
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@ -864,9 +794,9 @@ static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs,
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USXGMII_ADVERTISE_FDX);
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}
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static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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static void vsc9959_pcs_config(struct ocelot *ocelot, int port,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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struct felix *felix = ocelot_to_felix(ocelot);
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struct phy_device *pcs = felix->pcs[port];
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@ -898,16 +828,110 @@ static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
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pcs->supported);
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phy_advertise_supported(pcs);
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if (!phylink_autoneg_inband(link_an_mode))
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return;
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switch (pcs->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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vsc9959_pcs_init_sgmii(pcs, link_an_mode, state);
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vsc9959_pcs_config_sgmii(pcs, link_an_mode, state);
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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vsc9959_pcs_init_2500basex(pcs, link_an_mode, state);
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phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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vsc9959_pcs_init_usxgmii(pcs, link_an_mode, state);
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vsc9959_pcs_config_usxgmii(pcs, link_an_mode, state);
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break;
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default:
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dev_err(ocelot->dev, "Unsupported link mode %s\n",
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phy_modes(pcs->interface));
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}
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}
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static void vsc9959_pcs_link_up_sgmii(struct phy_device *pcs,
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unsigned int link_an_mode,
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int speed, int duplex)
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{
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u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN;
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switch (speed) {
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case SPEED_1000:
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if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_1000);
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break;
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case SPEED_100:
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if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_100);
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break;
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case SPEED_10:
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if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_10);
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break;
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default:
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phydev_err(pcs, "Invalid PCS speed %d\n", speed);
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return;
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}
|
||||
|
||||
if (duplex == DUPLEX_HALF)
|
||||
if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
|
||||
|
||||
phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
|
||||
phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
|
||||
}
|
||||
|
||||
/* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
|
||||
* clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
|
||||
* auto-negotiation of any link parameters. Electrically it is compatible with
|
||||
* a single lane of XAUI.
|
||||
* The hardware reference manual wants to call this mode SGMII, but it isn't
|
||||
* really, since the fundamental features of SGMII:
|
||||
* - Downgrading the link speed by duplicating symbols
|
||||
* - Auto-negotiation
|
||||
* are not there.
|
||||
* The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers
|
||||
* because the clock frequency is actually given by a PLL configured in the
|
||||
* Reset Configuration Word (RCW).
|
||||
* Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
|
||||
* AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
|
||||
* lower link speed on line side, the system-side interface remains fixed at
|
||||
* 2500 Mbps and we do rate adaptation through pause frames.
|
||||
*/
|
||||
static void vsc9959_pcs_link_up_2500basex(struct phy_device *pcs,
|
||||
unsigned int link_an_mode,
|
||||
int speed, int duplex)
|
||||
{
|
||||
u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) |
|
||||
ENETC_PCS_IF_MODE_SGMII_EN;
|
||||
|
||||
if (duplex == DUPLEX_HALF)
|
||||
if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
|
||||
|
||||
phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
|
||||
phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
|
||||
}
|
||||
|
||||
static void vsc9959_pcs_link_up(struct ocelot *ocelot, int port,
|
||||
unsigned int link_an_mode,
|
||||
phy_interface_t interface,
|
||||
int speed, int duplex)
|
||||
{
|
||||
struct felix *felix = ocelot_to_felix(ocelot);
|
||||
struct phy_device *pcs = felix->pcs[port];
|
||||
|
||||
if (!pcs)
|
||||
return;
|
||||
|
||||
if (phylink_autoneg_inband(link_an_mode))
|
||||
return;
|
||||
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
case PHY_INTERFACE_MODE_QSGMII:
|
||||
vsc9959_pcs_link_up_sgmii(pcs, link_an_mode, speed, duplex);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_2500BASEX:
|
||||
vsc9959_pcs_link_up_2500basex(pcs, link_an_mode, speed,
|
||||
duplex);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_USXGMII:
|
||||
phydev_err(pcs, "USXGMII only supports in-band AN for now\n");
|
||||
break;
|
||||
default:
|
||||
dev_err(ocelot->dev, "Unsupported link mode %s\n",
|
||||
|
|
@ -1374,7 +1398,8 @@ struct felix_info felix_info_vsc9959 = {
|
|||
.imdio_pci_bar = 0,
|
||||
.mdio_bus_alloc = vsc9959_mdio_bus_alloc,
|
||||
.mdio_bus_free = vsc9959_mdio_bus_free,
|
||||
.pcs_init = vsc9959_pcs_init,
|
||||
.pcs_config = vsc9959_pcs_config,
|
||||
.pcs_link_up = vsc9959_pcs_link_up,
|
||||
.pcs_link_state = vsc9959_pcs_link_state,
|
||||
.prevalidate_phy_mode = vsc9959_prevalidate_phy_mode,
|
||||
.port_setup_tc = vsc9959_port_setup_tc,
|
||||
|
|
|
|||
Loading…
Reference in New Issue